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MATERIALS AND DEVICES

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Material and device integration on silicon for advanced applications

The symposium aims to gather scientists working on monolithic and heterogeneous integration to expand silicon technology. It is an evolution of a symposia series that attracted a large number of attendees over the years. This research field paves the way towards highly functionalized Si-based technologies that can address challenges in our societies.

Scope:

Silicon remains the material of choice for manufacturing integrated circuit (IC), achieving an unbeaten level of system integration. Fundamental physical limits of Si present major obstacles for miniaturization (“More Moore”) and functionalization (“More than Moore”) of Si-based ICs. In parallel, new markets driven by societal needs – mobile & low power technologies, ultra-fast data communication, cognitive systems, application in life-sciences, new computing paradigms– will stem from technologies where the integration of alternative semiconductors and oxides on the mature Si technology platform can be successfully accomplished. The symposium will be devoted to highlighting novel breakthrough approaches that impact monolithic and heterogeneous integration on silicon baseline technology, either for CMOS applications (e.g. steep slope switches) or integrated photonics (e.g. monolithic lasers and silicon–organic hybrid modulators on a Si platform). The scope includes fundamental materials understanding, using novel integration schemes and/or state-of-the art modeling, or targeting new fields of application. The focus will be on the fabrication, characterization, and simulation (semi-empirical or ab-initio) of materials considered as non-standard for Si technology, such as strained SiGe, (Si)GeSn(C) etc.; compound semiconductors (III-V, II-VI); oxides, nitrides; and two-dimensional materials (graphene, BN, MX ). Contributions related to innovative hetero- 2 integration techniques (advanced heteroepitaxy, wafer bonding, microstructure printing, self-assembly etc.) will be encouraged. Finally, a particular attention will be given to devices and applications demanding an interdisciplinary approach such as RF applications, biomedical or environmental sensing concepts realized on a semiconductor platform (THz sensing and SERS with semiconductor plasmonics), and to materials innovations that aim at addressing new computing paradigms such as quantum and neuromorphic computation. The productive interaction across disciplines will help materials scientists to drive the exciting transition towards higher-value, highly functionalized Si-based microelectronics, supporting technology that can address today’s and tomorrow’s  societal needs.

Hot topics to be covered by the symposium:

Materials science, characterization and simulation:  

Group IV and compound semiconductors:

  • SiGe, Ge, and (Si)GeSn(C) 3D, 2D, 1D, and 0D heterostructures, semiconductors on insulators (SOI, GOI, SSOI, etc.).
  • Arsenides, phosphides, nitrides and antimonides, II-VI compounds

Oxides and nitrides: 

  • Functional perovskites, ZnO, GaN and heterostructures, oxides with resistive or metal insulator transition, topological insulators, piezoelectric materials

2 dimensional materials: 

  • Graphene and carbon nanotubes, Calchogenides, Boron Nitride

Structural and electronic modelling:

  • Atomistic/continuum simulations of strain release processes, growth simulations; multiscale approaches, ab initio/tight binding modelling of electronic and optical properties of films and nanostructures

Integration Techniques:  

Advanced heteroepitaxy: 

  • Selective growth or selective deposition on patterned substrate, epitaxial lateral overgrowth, self- assembly techniques

Layer Transfer and TSV

  • Wafer bonding, microstructure printing, die to wafer, Through Silicon Via techniques

Applications

Data processing and communication:

  • Quantum computing and communication, Advanced CMOS scaling; high-power / frequency devices; new transistor geometries, integrated photonics; IR and THz lasers; CMOS-Si electro-optical integration 

Life-Sciences application and environmental sensors

  • Semiconductor plasmonics for SERS, THZ sensing, gas sensors etc., integration with piezo-materials for MEMS-like sensors and opto-mechanics

Device Simulation

  • Advanced TCAD methods, nanoelectronic device simulation

List of invited speakers:

  • S. Abel (IBM, Switzerland) “Oxide  based modulators for Si photonic devices”
  • J.-N. Aqua (Institut des NanoSciences de Paris, France) “Heteorepitaxy on compliant substrates”
  • S. Ballandras (frec|n|sys, France) "Passive piezoelectric devices for RF filters & sensors"
  • M. Houssa (KUL, Belgium) “2D Materials for Nanoelectronics”
  • X. Jehl (INAC/CEA, France) "CMOS silicon spin qbit"
  • G. Katsaros (Institute of Science and Technology Austria) “Heavy hole states in Ge huts”
  • J. Knoch (RWTH Aachen, Germany) “2D materials on Group-IV-Platforms: Devices and Technology Challenges”
  • M. Camarda (CNR Catania, Italy) “Growth of  monocrystalline SiC on Si micrometric pillars”
  • R. Gull (Synopsys) “TCAD: Present State and Future Challenges for advanced CMOS nodes”
  • M. Myronov (U Warwick, UK) “High mobility Ge channels on Si: Fabrication and Applications”
  • J.-P. Raskin (UC de Louvain, Belgium) "Silicon devices for high frequency applications"
  • H. Sigg (PSI, Switzerland) “Strained Ge Microbridges”
  • A. Spiesser (AIST, Japan) “Efficient spin transport in Si devices using magnetic contacts”
  • E. Tournie (CNRS/Univ. Montpellier, France) “III-Sb based lasers on Si”,
  • M. Zöllner (IHP, Germany) “Advanced materials characterization via synchrotron diffraction”

List of scientific committee members:

  • F. Alibart (France)
  • H. Bhaskaran (UK)
  • S. Chiussi (Spain)
  • N. Curson (UK)
  • J. Gómez Rivas (The Netherlands)
  • G. Larrieu (France)
  • D. Marris-Morini (France)
  • O. Nakatsuka (Japan)
  • G. Niu (China)
  • G. Saint-Girons (France)
  • A. Seeds (UK)
  • G. Scappucci (The Netherlands)
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08:45 Symposium Introduction    
 
M-1: SYMPOSIUM PLENARY : Inga A. Fischer
09:00
Authors : Sylvain Ballandras
Affiliations : Frec[n]sys

Resume : Passive acousto-electric devices are massively designed and manufactured for various radio-frequency applications and more specifically for mobile communicating setups. Filters and resonators based on surface acoustic wave (SAW) or bulk acoustic wave (BAW) devices are widely investigated and yield numerous academic as well as industrial developments. SAW filters were both implemented for so-called intermediate frequencies (IF - corresponding to VHF) and radio-frequencies (RF ~ UHF) used in mobile pĥones during the 90s but are almost exclusively developed for RF stages and modules (ranging from about 800 MHz to 3 GHz). On the other hand, the capability of these devices to be remotely controlled without on-board power supply has generated an increasing activity during the passed 15 years. Although based on same principles, filters and sensors based on these devices do not meet the same specifications and may substantially differ considering their actual operation. In particular, SAW and BAW used for filters generally requires electromechanical coefficients, velocities, band gaps that allow for achieving various relative frequency bands and must be strictly adapted to the filter spectral operation. The temperature sensitivity of the wave must be however reduced at the minimum possible value to answer the demand for band separation and juxtaposition for duplexer and modern RF modules. For sensors, depending on the physical parameter to monitor, temperature drift may be maximized or minimized as well, but the coupling and velocity properties may be less important than robustness to environmental conditions or compactness. These aspects will be discussed in this talk. These devices have made an extensive use of standard single-crystal substrates such as quartz, lithium tantalate and niobate. However, new challenges have pushed the development of alternative crystals (Langasite and related materials, GaPO4, BST, etc.) and also composite wafers based on piezoelectric films on Silicon Sapphire and other non piezoelectric substrates. This presentation introduces basic principles of radio-frequency acoustic devices and the various structures usually implemented for filters, resonators and sensors. Several examples allows for illustrating the implementation of these devices and a focus is then proposed on material development for wireless SAW/BAW setups. We provide an outlook of state-of-the-art wireless applications, with a discussion on further developments to address future RF communication challenges.

M.1.1
09:30
Authors : Aurelie Spiesser 1, Hidekazu Saito 1, Yuichi Fujita 2, Shinya Yamada 2-3, Kohei Hamaya 2-3, Shinji Yuasa 1, Ron Jansen 1
Affiliations : 1 National Institute of Advanced Industrial Science and Technology (AIST), Spintronics Research Center, Tsukuba, Japan 2 Department of Systems Innovation, Graduate School of Engineering Science, Osaka University, Osaka, Japan 3 Center for Spintronics Research Network, Graduate School of Engineering Science, Osaka University, Osaka, Japan

Resume : The integration of semiconductors (SCs) and magnetic materials offers a promising route to develop the next generation of energy-efficient information technology and go beyond CMOS. The spin-MOSFET, whose source and drain are ferromagnetic, is one the key devices in SC spintronics. Its operation is based on the injection, transport and detection of spin-polarized carriers in a lateral SC channel. Silicon, owing to its compatibility with the existing CMOS technology and its long spin coherence, is the most suitable candidate to develop spin-based SC devices. Although the electrical injection, transport and detection of spins in silicon have been achieved, the induced spin accumulation was much smaller than expected and desired, limiting the potential impact of Si-based spintronics devices. Here, we have fabricated Si lateral devices with Fe/MgO magnetic tunnel contacts and demonstrated efficient spin injection, transport and detection in a Si channel up to room temperature. Non-local spin-valve and Hanle measurements performed at various biases and temperatures indicate that the tunnel spin polarization of Fe/MgO reaches 53 % at 10 K, which is the highest value reported to date. We also show that we can significantly enhance the spin accumulation in Si by designing a spin injector with a width comparable to or larger than the spin-diffusion length in the Si. The experimental data are in excellent agreement with numerical calculations that are based on the standard theory for spin injection and diffusion in a non-magnetic material. From our results, we deduce that a spin accumulation of more than 10 meV is present in the Si channel at 10 K, proving that large carrier spin polarization can be created in Si-based spintronics devices.

M.1.2
10:00
Authors : E. Tournié,1 L. Cerutti,1 J.B. Rodriguez,1 A. Castellano,1 M. Niehle,3 G. Patriarche,2 A. Trampert3
Affiliations : 1Université de Montpellier, CNRS, IES, UMR 5214, F-34000 Montpellier, France 2CNRS, Université Paris-Sud, C2N, UMR 9001, F-91460 Marcoussis, France 3Paul-Drude-Institut für Festköperelektronik, D-10117 Berlin (Germany)

Resume : The availability of integrated light sources is the key technology for the whole Si photonics industry. The direct epitaxial growth of III-V lasers on Si-photonics circuits appears as the most promising, cost-effective and versatile approach. III V heteroepitaxy on Si has for long proven difficult due to the conjunction of large lattice-, thermal- and polarity- mismatches. However, much progress has been made in the recent years on the understanding and mastering of these issues. The first issue to deal with when growing III-Vs on Si is the substrate preparation. Indeed, III-V epitaxial reactors are generally not adapted to in situ Si de-oxidation which requires very high temperatures and clean environment. The lattice mismatch between GaSb and Si is as huge as ~13%. The nucleation process is thus of uppermost importance. Inserting a thin AlSb nucleation layer, the thickness of which depends on the growth temperature, results in the best material quality and X-ray rocking curves linewidth comparable to that of GaAs or Ge on Si (mismatch ~ 4 %) are achieved. Transmission electron microscopy (TEM) investigations reveal the formation of a network of interfacial misfit dislocations which very efficiently relieve the strain, together with micro-twins and antiphase domain boundaries. Continuous-wave lasing has been achieved above room-temperature between 1.5 and 2.X µm with GaIn(As)Sb/AlGaAsSb laser diodes grown on such buffer layers. Work partly supported by the French ANR (project OPTOSi, ANR-12-BS03-002 and project ANTIPODE, ANR-14-CE26-0014) and program on "Investments for the Future" (EquipEx EXTRA, ANR-11-EQPX-0016).

M.1.3
10:30 Coffee Break    
 
M-2: Optoelectronic Devices : Clément Merckling
11:00
Authors : Stefan Abel (1), Felix Eltes (1), Kristy J. Kormondy (2), Daniele Caimi (1), Bert J. Offrein (1), and Jean Fompeyrine (1)
Affiliations : (1) IBM Research - Zurich, Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland (2) Department of Physics, The University of Texas at Austin, Austin, TX, USA

Resume : Silicon photonics now matured as a CMOS compatible technology for high-speed optical communication. Active electro-optical switches and modulators are key components of such integrated optical circuits. For long-haul communication, such components typically rely on the linear electro optical effect in bulk lithium niobate. Contrary, such effect cannot be exploited in silicon photonics due to the absence of the Pockels-effect. In our work, we will discuss the co-integration of silicon photonics with novel, nonlinear-optical materials for active electro-optical devices. We focus on barium titanate (BTO) epitaxially deposited on silicon substrates [1] and show the influence of the BTO materials properties such as porosity on the electro-optical performance [2]. Successively, we will present a BTO/Si-waveguide platform with passive and active devices, such as waveguides with low losses of <6 dB/cm [3], resonators with quality factors of >20’000, active switches with low-power tunability of 4 W/nm [4] and high-speed electro-optical modulators. Finally, we will discuss the prospects of the BTO/Si waveguide technology for applications beyond optical communication, such as photonic neuronal networks for pattern recognition. [1] S. Abel et al. Nat. Commun., vol. 4, p. 1671, 2013. [2] K. J. Kormondy et al. Nanotechnology, vol. 28, p. 75706, 2017. [3] F. Eltes et al. ACS Photonics, vol. 3, p. 1698, 2016. [4] S. Abel et al. J. Light. Technol., vol. 34, no. 8, pp. 1688–1693, Apr. 2016.

M.2.1
11:30
Authors : Andrés M. Raya (1), José M. Llorens (1), David Fuster (1), Jerónimo Buencuerpo (2)
Affiliations : (1) IMM - Instituto de Microelectrónica de Madrid (CNM-CSIC), 28760 Tres Cantos, Madrid, Spain.; (2) Universidad Complutense de Madrid, Facultad de Ciencias Físicas, Departamento de Óptica, Plaza de las Ciencias 1, 28040 Madrid, Spain.

Resume : III-V semiconductor nanowires (NWs) are promising candidates for the next generation of optoelectronic devices due to their unique properties such as enhanced light absorption. The axial relaxation of the strain allows the combination of lattice mismatched materials like GaAs and Si. In most practical cases, the absorption in the nanowires is challenging to measure because NWs are fabricated on opaque substrates. The possibility of estimating the absorption from the reflectance has been proven [1], showing the interest in this optical characterization. In this work, series of samples consisting on self-catalyzed GaAs NWs on Si(111) were grown by Molecular Beam Epitaxy following the Vapor-Liquid-Solid mechanism. We changed the growth temperature in an interval between 555 and 630 ºC as well as the thickness of the oxide layer of the substrate. As a consequence, we found a dependence of the geometrical characteristics of the NWs with the growth conditions. We have measured the reflectivity and correlated it with the dimensions, density and proportion of vertically oriented NWs. Finally, the experimental values were compared with those obtained by theoretical calculations [1,2] and were supported by an in-depth SEM analysis. [1] N. Anttu et al., Opt. Lett., 38, 1449-1451 (2013) [2] R.A. Street et al., Nano Lett., 9 (10), 3494-3497 (2009)

M.2.2
11:45
Authors : J. Aubin* 1, J.M. Hartmann 1, V. Reboud 1, A. Gassenq 2, N. Pauc 2, L. Milord 1, J.L. Rouvière 2, E. Robin 2, D. Cooper 1, V. Delaye 1, N. Mollard 2, Q. M. Thai 2, M. Bertrand 1, K. Guilloy 2, D. Rouchon 1, J. Rothman 1, T. Zabel 3, F. Armand Pilon 3, H. Sigg 3, A. Chelnokov 1 and V. Calvo 1.
Affiliations : 1 Univ. Grenoble Alpes, CEA-LETI, Minatec, 17 rue des Martyrs, 38000, Grenoble, France; 2 Univ. Grenoble Alpes, CEA, INAC, PHELIQS, F-38000 Grenoble; 3 Laboratory for Micro- and Nanotechnology, Paul Scherrer Institute, 5232, Villigen, Switzerland.

Resume : The epitaxy of high Sn content (i.e. 16% and 13%) GeSn alloys in a 200 mm industrial Reduced Pressure - Chemical Vapor Deposition tool has been investigated. A specific Step-Graded approach has been set up to grow thick, high Sn content GeSn layers on Ge buffers, themselves on Si (001) substrates. The benefit of this step graded approach, in terms of crystalline quality and surface morphology, has been demonstrated using X-Ray Diffraction, Atomic Force Microscopy and Transmission Electron Microscopy. A gradual relaxation of the built-in compressive strain occurred in the grading (Macroscopic Degree of Strain Relaxation R ~ 70% in the top layers), minimizing Sn segregation and precipitation. Photoluminescence showed that our Ge0.87Sn0.13 and Ge0.84Sn0.16 stacks have a direct band gap. Optically pumped laser emission at 2.6 µm (for 13% of Sn) and 3.1 µm (for 16% of Sn) was obtained in suspended GeSn micro-disks (after etching into pillars of the underlying Ge buffers). The lack of residual compressive strain at the free-standing edges of the micro-disks, which increases the directness of the bandgap (Whispering Gallery Mode propagation of the light), and the very high quality of the Ge0.84Sn0.16 cavities led to laser operation up to 180 K at an emission wavelength of 3.1 µm, with a lasing threshold of 377 kW/cm² at 25K.

M.2.3
12:00
Authors : Amna Safdar, Yue Wang and Thomas F Krauss
Affiliations : Department of Physics, University of York

Resume : Nanoscale structures introduce new ways for manipulating light coupling and trapping at the subwavelength scale. Light trapping structures that can effectively control and enhance light absorption such as nanowires[1], inverted nanopyramids[2], quasi-random patterns[3], nanospikes and nanocones[4] have all been reported, although mainly in the optical domain, with a few exceptions. In particular, structures are known as “black silicon” exhibit nearly zero reflection over a broad-spectrum range. The challenge is to incorporate such structures into real devices and not to compromise the optical enhancement by electrical losses such as surface recombination. Since black silicon devices exhibit large surface areas, minimising surface recombination is particularly difficult. For example, the black silicon solar cells reported thus far have yet not been able to compete with conventional silicon devices. Jihun Oh et al. have reported an 18.2% efficient interdigitated back contact (IBC) black silicon device[6]. They report that the doping profile is an important parameter for determining the dominant recombination process. They find that surface recombination only dominates for low doping density otherwise efficiency limitation is mainly due to Auger recombination. In contrast, Hele Sevin et al. report a 22.1% black silicon IBC device by overcoming surface recombination through a conformally deposited layer of alumina[7]. Here, we demonstrate the fabrication of quasi-random structures that have similar optical properties as black silicon and realise them by both wet and dry processing. We present a quantitative comparison of these structures both in the optical and electrical domain, assessing the impact of plasma etching by comparing the same nanostructures made by wet etching. Furthermore, it is interesting to understand whether the taper angle of the wet etched structure improves the antireflective property compared to the vertical walls achieved by dry etching. Ultimately, we hope to address the question whether we can use nanostructuring to improve the optical performance of solar cell devices without compromising their electrical efficiency. 1. Garnett, E. & Yang, P. Light trapping in silicon nanowire solar cells. Nano Lett. 10, 1082–7 (2010). 2. Zhou, S. et al. Wafer-Scale Integration of Inverted Nanopyramid Arrays for Advanced Light Trapping in Crystalline Silicon Thin Film Solar Cells. doi:10.1186/s11671-016-1397-6 3. Martins, E. R. et al. Deterministic quasi-random nanostructures for photon control. Nat. Commun. 4, 2665 (2013). 4. Wang, K. X., Yu, Z., Liu, V., Cui, Y. & Fan, S. Absorption enhancement in ultrathin crystalline silicon solar cells with antireflection and light-trapping nanocone gratings. Nano Lett. 12, 1616–1619 (2012). 6. Oh, J., Yuan, H.-C. & Branz, H. M. An 18.2%-efficient black silicon solar cell achieved through control of carrier recombination in nanostructures. Nat. Nanotechnol. 7, 743–748 (2012). 7. Savin, H. et al. Black silicon solar cells with interdigitated back contacts achieve 22.1% efficiency. Nat. Nanotechnol. 10, 1–6 (2015).

M.2.4
12:15
Authors : J. M. Ramírez(1), V. Vakarin(1), Q. Liu(1), A. Ballabio(2), J. Frigerio(2), P. Chaisakul(3), D. Chrastina(2), X. Le Roux(1), C. Gilles(4), G. Maisons(4), M. Carras(4), L. Vivien(1), G. Isella(2), D. Marris-Morini(1)
Affiliations : (1) Centre de Nanosciences et Nanotechnoglogies, Univ. Paris-Sud, CNRS UMR 9100, Université Paris Saclay, Bâtiment 220, 91405 Orsay Cedex, France; (2) L-NESS, Politecnico di Milano, Polo di Como, Italy (3) Department of Physics, Faculty of Science, Kasetsart University, Bangkok 10900, Thailand (4) MirSense, 86 Rue de Paris, 91400 Orsay, France delphine.morini@u-psud.fr

Resume : The extension of silicon photonics towards the mid infrared (mid-IR) spectral range has recently attracted a lot of attention. The development of photonic devices operating at these wavelengths is crucial for many applications including environmental and chemical sensing, astronomy and medicine. Recent works regarding the development of Ge-rich SiGe waveguides and interferometric devices on silicon will be presented. In particular, low-loss waveguides with good butt-coupling performance over a wide range of mid-IR wavelengths (from 5.5 µm up to 8.5 µm) will be shown, hence providing a key building block for further development of mid-infrared photonic integrated circuits. Specifically the design, fabrication and characterization of ultra-wideband couplers, resonators, and Mach Zehnder interferometers will be disclosed. These results provide a solid basis to develop a competitive mid-IR integrated platform which could potentially exploit the complete Ge transparency window, up to λ ≈ 15 µm.

M.2.5
12:30 Lunch Break    
 
M-3: Materials for Opto- and Nanoelectronics I : Francesco Montalenti
14:00
Authors : Hans Sigg
Affiliations : Paul Scherrer Institut, Laboratory for Micro and Nanotechnology, Switzerland

Resume : New Si optical platforms harnessing many of the core capabilities of CMOS are rapidly changing the landscape of photonics. These platforms carry many basic components such as detectors, modulators and resonators, central for the development of optical data processing, linking and sensing applications. Seemingly, not easy to be realized in the indirect band gap group IV system is a laser light-source integrated with the well-established current Si based CMOS-electronics process technologies. Here, we will discuss forthcoming challenges on the way of a practical direct band gap Ge laser device1. Key issues involve the carrier inversion lifetime, parasitic absorption and the intravalley scattering to the L-levels, as revealed from recent synchrotron based pump und probe investigations. We present uniaxial tensile strained suspended GeOI micro-bridges2 combined with strain conserving cavities formed by parabolic mirrors in a corner cube configuration. We show the multimode cavity enhanced photo-luminescence (PL) up to 5 µm and a loss analysis of the mode spectrum. These results will be benchmarked by the lasing characteristics obtained at low temperature of optically pumped GeSn directly grown on Ge virtual substrate on silicon3. 1 R. Geiger et al. (2015). doi:10.3389/fmats.2015.00052. 2 M.J. Süess et al. (2013). NP. doi:10.1038/nphoton.2013.67. 3 S. Wirths et al. (2015). NP. doi:10.1038/nphoton.2014.321.

M.3.1
14:30
Authors : Sebastiano De Cesari, Elisa Vitiello, Emanuele Grilli, Fabio Pezzoli
Affiliations : Sebastiano De Cesari; Elisa Vitiello; Emanuele Grilli; Fabio Pezzoli: LNESS and Dipartimento di Scienza dei Materiali, Università degli Studi di Milano Bicocca, via R. Cozzi 55, I-20125 Milan, Italy.

Resume : The ability to steer polarized optical fields is recognized as a central issue in photonics. Current approaches primarily rely on strong external magnetic fields or optical delay modulators, and do not allow the compact and monolithic design required for integrated architectures. Here we overcome such an obstacle by proposing a simple scheme based on engineered spin-dependent carrier dynamics. In particular, exploiting the multi-valley feature of the Germanium conduction band, we achieve all-optical control of chiral light emission, unveiling the key role of optical pumping. We investigate the state of the polarization of the direct-gap photoluminescence in bulk Ge and we provide an overview of the processes governing the recombination of carriers in the Γ valley. Our results anticipate spin-enhanced optoelectronic functionalities and provide a step forward towards the implementation of novel polarized light sources, such as Ge-based spin LEDs and spin lasers monolithically integrated on Si.

M.3.2
14:45
Authors : A. Ballabio 1, J. Frigerio1, K. Gallacher2, V. Giliberti3, L. Baldassarre3, R. Millar2, R. Milazzo4, L. Maiolo5, A. Minotti5, F. Bottegoni6, P. Biagioni6, D.J. Paul2, M. Ortolani3, A. Pecora5, E. Napolitani4 and G. Isella1
Affiliations : 1 L-NESS, Dipartimento di Fisica, Politecnico di Milano, Polo di Como, Via Anzani 42, I-22100 Como, Italy; 2 School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LT, United Kingdom; 3 Dipartimento di Fisica, Sapienza Università di Roma, Piazzale Aldo Moro 5, I-00185 Rome, Italy; 4 Dipartimento di Fisica e Astronomia, Università di Padova and CNR-IMM Matis, Via Marzolo 8, I-35131 Padova, Italy; 5 CNR-IMM, Via del Fosso del Cavaliere 100, 00133 Roma, Italy; 6 Dipartimento di Fisica, Politecnico di Milano, piazza Leonardo da Vinci 32, I-20133 Milano, Italy;

Resume : High n-type doping in germanium is essential for many electronic and optoelectronic applications especially for high performance Ohmic contacts, lasing and mid-infrared plasmonics. We report on the combination of in situ doping of Ge-on-Si epilayers and excimer laser annealing to improve the activation of phosphorous in germanium. An activated n-doping concentration of 8.8×10^(19) cm^(–3) has been achieved starting from an incorporated phosphorous concentration of 1.1×10^(20) cm^(–3). Secondary ion mass spectrometry measurements indicate that the box-like profile of as-deposited epilayers is preserved during the annealing treatment. Infrared reflectivity data fitted with a multi-layer Drude model indicate good uniformity in carrier concentration over a 350 nm thick layer. Photoluminescence demonstrates clear bandgap narrowing and an increased ratio of direct to indirect bandgap emission confirming the high doping densities achieved. The residual thermal in-plane strain of +3.7×10^(-3), as measured by Raman spectroscopy, exceeds the typical strain values of 2-2.5×10^(-3) achievable by conventional annealing methods, favoring the electron population of the Gamma-valley. Preliminary results achieved by optimizing both the growth procedure and the annealing treatment show that carrier concentration exceeding 1×10^(20) cm^(-3) can be obtained. [1] R. Pillarisetty, Nature 479, 324 (2011) [2] L. Baldassarre et al., Nano Lett. 15, 7225 (2015) [3] J. Frigerio et al., Phys. Rev. B 94, 085202 (2016)

M.3.3
15:00
Authors : Stefan Bechler, Inga A. Fischer, Akant Sengül, Michal Kern, Roman Körner, Michael Oehme, Jörg Schulze
Affiliations : Institute for Semiconductor Engineering and Center for Integrated Quantum Science and Technology, Universität Stuttgart, Pfaffenwaldring 47, Stuttgart, 70569, Germany; Institute for Semiconductor Engineering and Center for Integrated Quantum Science and Technology, Universität Stuttgart, Pfaffenwaldring 47, Stuttgart, 70569, Germany; Institute for Semiconductor Engineering and Center for Integrated Quantum Science and Technology, Universität Stuttgart, Pfaffenwaldring 47, Stuttgart, 70569, Germany; Institute for Physical Chemistry and Center for Integrated Quantum Science and Technology, Universität Stuttgart, Pfaffenwaldring 55, Stuttgart, 70569, Germany; Institute for Semiconductor Engineering and Center for Integrated Quantum Science and Technology, Universität Stuttgart, Pfaffenwaldring 47, Stuttgart, 70569, Germany; Institute for Semiconductor Engineering and Center for Integrated Quantum Science and Technology, Universität Stuttgart, Pfaffenwaldring 47, Stuttgart, 70569, Germany; Institute for Semiconductor Engineering and Center for Integrated Quantum Science and Technology, Universität Stuttgart, Pfaffenwaldring 47, Stuttgart, 70569, Germany

Resume : Spintronics is an evolving concept for beyond CMOS-devices. In many of these concepts, spin polarized charge carriers get injected from a ferromagnetic contact into a semiconductor channel. Germanium is a good candidate for the semiconductor material due to the high electron and hole mobilities which lead to long spin lifetimes. Germanium itself can be easily integrated into the Si-platform. The ferromagnetic contact material should also be capable of being integrated into the Si-platform. In this work the formation of Mn5Ge3 on tensile strained Ge channels is investigated. The Ge channels are grown on Si (111) substrates by Molecular Beam Epitaxy (MBE). The fabrication of Mn5Ge3 can be carried out similarly to a silicidation process by evaporating Mn on Ge (111) and annealing to form the ferromagnetic Mn5Ge3 contact material. To investigate the formation of Mn5Ge3 we varied annealing parameters such as the ramp up time and the maximum temperature. Measurements of the magnetization using a superconducting quantum interference device show a ferromagnetic behavior for all samples, however, coercivity and remanescence vary. Using Mn5Ge3 as contact material, 3-terminal-devices using highly-doped Ge-channels are fabricated and Hanle-measurements are performed.

M.3.4
15:15
Authors : Sang Hoon Kim, Gyungock Kim
Affiliations : Electronics and Telecommunications Research Institute; Electronics and Telecommunications Research Institute

Resume : The growth of high-quality polycrystalline germanium on oxide is of interest to chip-level electronic-photonic integration on silicon wafer. High-quality polycrystalline germanium on silicon-oxide facilitates the fabrication of germanium devices in various applications including the back-end-of-line photonic device manufacturing. In this work, we present the large-grained polycrystalline germanium growth on oxide using reduced pressure chemical vapor deposition (RPCVD), which can have advantages in future device fabrications. In order to increase the polycrystalline germanium (poly-Ge) grain size for the reduction of the grain boundary density, we employed the selective growth technique and thin poly-silicon interlayer. Poly-Si interlayer and poly-Ge were sequentially grown in silicon-oxide trenches. The grain size of poly-Ge was investigated with the growth parameters, such as growth temperature, working pressure and growth rate. The crystal states of the grown germanium layers were characterized with high resolution X-ray diffraction (HRXRD) measurement, and the grain size was measured using electron backscattering diffraction (EBSD) and transmission electron microscopy (TEM). The measured grain size of the grown poly-Ge shows strong dependence on the crystalline quality of the poly-Si interlayer, indicating that much improvement on crystalline quality of poly-Ge can be achieved with proper optimization in our RPCVD selective growth technique.

M.3.5
15:30 Coffee Break    
 
M-4: Nanopatterning and SiC Growth : Didier Landru
16:00
Authors : M. Camarda
Affiliations : Institute of Microsystem and Microelectronics, Italian National Research Council, IMM-CNR. Laboratory of Micro- and Nanotechnologies, Paul Scherrer Institute, LMN-PSI.

Resume : Silicon Carbide (SiC) is a wide bandgap material with high breakdown fields, high thermal conductivity and high saturated drift velocities, with potential applications in high power devices and microelectromechanical systems (MEMS) in harsh environments. It has up to 200 different stable crystal structures (polytypes) all having different band gap and thus different electrical properties. Among the different polytypes, the cubic structure, referred as 3C-SiC, is the most thermodynamically stable at low growth temperatures (1100-1600 C), this allowing it to be hetero-epitaxially grown on Silicon substrates. The use of large-area substrates offers the possibility of economical and low-cost batch processing, which makes 3C-SiC more attractive for sensor and device applications and, given its small bandgap (when compared to the 4H-SiC polytype) of 2.36eV, for medium voltage applications (between 600 and 1600V). Though possible, the SiC/Si hetero-epitaxy suffers from the large lattice and thermal mismatch of the two semiconductors, 20% and 8% respectively, which give rise to both defects and stress. At the talk I will present the different defects, generated at the interface and into the film, and the associated stress as function of the crystal orientations and growth properties, and how they can be potentially reduced by the use of “compliance substrates”, with specific focus on growths on micrometric Silicon pillars.

M.4.1
16:30
Authors : Rami Khazaka1-2, Jean François Michaud1, Philippe Vennéguès2, Daniel Alquier1, Marc Portail2
Affiliations : Université François Rabelais, Tours, GREMAN, CNRS-UMR 7347, 16 rue Pierre et Marie Curie, BP 7155, 37071 Tours Cedex 2, France; CRHEA, CNRS-UPR10, rue Bernard Gregory, 06560 Valbonne, France

Resume : The cubic polytype of silicon carbide (3C-SiC) is an interesting wide band gap material with outstanding properties, very promising for designing Micro-Electro-Mechanical Systems (MEMS) devices operating in harsh environment where Si-based devices reveal a shortage in their performance. The fabrication of suspended micromachined membranes triggers the interest for several applications such as pressure, tactile, flow, microfluid and acoustic sensors. In particular, 3C-SiC based membranes are advantageous for such devices operating in harsh and corrosive environments. In this contribution, we describe an approach that enables direct 3C-SiC membrane release, in real time, as the membrane grows. This new approach stems from controlling and exploiting the presence of voids in a Si epilayer, in stark contrast to the conventional view of voids as defects. This straightforward technique is expected to markedly simplify the fabrication process of membranes by reducing the fabrication duration and cost. In the presentation, we will first describe the growth of the complete 3C-SiC/Si/3C-SiC heterostructure on Si substrates, required for 3C-SiC membrane fabrication. The growth conditions and the defects in each layer will be commented based on TEM, XRD, SEM and AFM observations. Later on, the novel method for membrane fabrication will be presented. Finally, the advantages of this unprecedented technique compared to conventional techniques will be highlighted.

M.4.2
16:45
Authors : M. Portail, L. Nguyen, R. Khazaka, R. Dagher, A. Michon, M. Zielinski, Y. Cordier
Affiliations : CNRS-CRHEA, Université Côte d’Azur, Rue Bernard Grégory, 06560 VALBONNE, France; NOVASiC, Savoie Technolac, Arche Bat 4, BP267, 73375 LE BOURGET DU LAC, France; CEA, LETI, MINATEC Campus, F-38054 GRENOBLE, France;

Resume : The growth of SiC on AlN thin films is challenging in many aspects. Indeed, the benefit of handling properly crystalline SiC/AlN heterostructures could open the way toward the design of innovative heterostructures, taking advantages both of the electrical and mechanical properties of SiC and AlN. Our group has recently communicated on the potential advantages of fully crystalline SiC membranes on Si substrates (R. Khazaka et al. APL 110, 081602 (2017)), but some applications require to electrically isolate the upper and lower SiC membranes. In this perspective, AlN is very promising regarding its high bandgap and its ability to be grown on SiC/Si templates. Nevertheless, we have to face different major concerns as SiC growth requires high temperatures and gas environment which could severely damage the AlN. In this presentation, we show the routes we adopt to grow, by CVD, cubic SiC on AlN(0001) thin films. We use either AlN thin films grown by MBE on Si(111) substrates or 3C-SiC/Si(111) CVD templates. We investigate the influence of the initial thermal ramp up, preceding the SiC growth. It is shown that the preservation of a surface suitable for SiC growth requires the use of carbon- or silicon- rich precursor gases diluted in nitrogen. We present also the characteristics of the SiC films grown on the AlN films according to the growth conditions. It is shown that, due to the site competition effect between C and N, a strong self-doping can occur during the growth.

M.4.3
17:00
Authors : A. Novikau, S. Prokopyev, A. Batulev, M. Lobanok, P. Gaiduk
Affiliations : Department of Physical electronics and nanotechnology, Belarusian State University, Minsk | novikaua@bsu.by

Resume : Silicon carbide is very attractive material for microelectronic integrated circuits production due to chemical, electrical properties and also huge radiation and thermal durability. Silicon carbide substrates are expensive for serial production and it schould be found a method to grown defects free epitaxial silicon carbide layers on top of cheep silicon substrates. Silicon carbide layers grown directly on silicon are defect-riched due to significant lattice misfit and difference of thermal expansion coefficient. Additionally, formation of porous layer under the silicon carbide results in decrease of elastic strain and consequently improves the structural quality of silicon carbide. One can suggest that additional growth of silicon or silicon-germanium patterned layers during SiC growth will leads to noticeable decrease of growth temperature as well as improvement of the quality of silicon carbide. The main goal of the present work is investigation of high temperature carbidization process of silicon wafers with epitaxial patterned buffer layers.

M.4.4
17:15
Authors : Thierno-Moussa Bah 1&2, Stanislav Didenko 2, Jean-François Robillard 2, Stephane Monfray 1, Thomas Skotnicki 1, Emmanuel Dubois 2
Affiliations : 1 : STMicroelectronics - 850 rue jean Monnet 38920 Crolles (France) 2 : Univ. Lille, CNRS, Centrale Lille, ISEN, Univ. Valenciennes, UMR 8520 - IEMN, F-59000 Lille, France

Resume : Developing silicon based thermoelectric generators is subject to high interest in the thermoelectric energy harvesting community. Compared to conventional materials used for commercial thermoelectric generators, silicon has the advantages to be the most wide spread semi-conductor material, environmentally less harmful and benefits from existing facilities and processing technologies developed for low cost mass production. However, the high thermal conductivity of bulk silicon makes it a very poor thermoelectric material especially for near room temperature applications. Hence, thermal conductivity reduction is the key to upgrade silicon as an efficient thermoelectric material. Efforts toward thermal conductivity reduction are oriented toward reducing the phononic heat transport, which is the dominant contribution. This reduction can be achieved by reducing the phonon mean free path and/or the phonon group velocity e.g. by use of thin films [1], nanowires [2], addition of impurities [3], silicon nano-patterning [4]… . Previous works have shown that periodical holes structures called phononic crystals are able to downscale further the thermal conductivity with minor impact on the electrical conductivity [5]. The combination of the thin film and the phononic crystal enables reaching a thermal conductivity from 34 W∙m^(-1)∙K^(-1) [6] to even as low as 2 W∙m^(-1)∙K^(-1) [4]. In this paper we focus on the potential thermoelectric properties improvement of silicon by means of a planar phononic thin silicon film based thermoelectric generator. The expected performance is benchmarked with respect to existing commercial thermoelectric generator. We performed a FEM benchmarking of our optimized thin silicon based TEG with the commercial Micropelt’s TEG [7], [8] for 20 W∙m^(-1)∙K^(-1) and 4 W∙m^(-1)∙K^(-1) hypotheses as silicon’s thermal conductivity, near room temperature range and for two cooling conditions : natural convection without heat sink and natural convection with a small-capacity heat sink. Results show an improved exploitation of the thermal gradient into the thermoelectric material due the planar architecture thus leading to a maximized harvested energy even without need for massive heat sink. Those results open perspectives in the field of autonomous sensor nodes based on low cost and scaled silicon material production. Bibliography: [1] M. Haras et al., « Fabrication of integrated micrometer platform for thermoelectric measurements », in 2014 IEEE International Electron Devices Meeting, 2014, p. 8.5.1-8.5.4. [2] A. I. Hochbaum et al., « Enhanced thermoelectric performance of rough silicon nanowires », Nature, vol. 451, no 7175, p. 163‑167, janv. 2008. [3] J.-H. Lee, G. A. Galli, et J. C. Grossman, « Nanoporous Si as an Efficient Thermoelectric Material », Nano Lett., vol. 8, no 11, p. 3750‑3754, nov. 2008. [4] J. Tang et al., « Holey Silicon as an Efficient Thermoelectric Material », Nano Lett., vol. 10, no 10, p. 4279‑4283, oct. 2010. [5] J.-K. Yu, S. Mitrovic, D. Tham, J. Varghese, et J. R. Heath, « Reduction of thermal conductivity in phononic nanomesh structures », Nat Nano, vol. 5, no 10, p. 718‑721, oct. 2010. [6] M. Haras et al., « Fabrication of Thin-Film Silicon Membranes With Phononic Crystals for Thermal Conductivity Measurements », IEEE Electron Device Letters, vol. 37, no 10, p. 1358‑1361, oct. 2016. [7] H. Bottner, « Thermoelectric micro devices: current state, recent developments and future aspects for technological progress and applications », in Twenty-First International Conference on Thermoelectrics, 2002. Proceedings ICT ’02, 2002, p. 511‑518. [8] H. Bottner, « Micropelt miniaturized thermoelectric devices: small size, high cooling power densities, short response time », in ICT 2005. 24th International Conference on Thermoelectrics, 2005., 2005, p. 1‑8.

M.4.5
 
Poster Session : I. A. Fischer, D. Landru, C. Merckling, F. Montalenti
18:00
Authors : Sawsan Almohammed,a,b, Sarah Olabisi Oladapo,a, Kate Ryan,a,b, Andrei L. Kholkin,c James H. Ricea, and Brian J. Rodrigueza,b
Affiliations : a,School of Physics, University College Dublin, Belfield, Dublin 4, Ireland b, Conway Institute of Biomolecular and Biomedical Research, University College Dublin, Belfield, Dublin 4, Ireland c, Department of Physics & CICECO-Aveiro Institute of Materials, 3810-193 Aveiro, Portugal and Institute of Natural Sciences, Ural Federal University, 620000 Ekaterinburg, Russia

Resume : Self-assembled diphenylalanine (FF) peptide nanotubes (PNTs) have attracted significant attention due to their well-ordered supramolecular structure and wide range of functional capabilities that may enable potential nanobiotechnology applications. However, self-assembled PNTs are generally inhomogenous at the macroscale, which has limited their potential use. Reproducibly controlling the assembly and alignment of PNTs is therefore critical to enable the widespread use of PNTs, e.g., in sensing applications. In this study, a surface patterning technique based on UV/ozone exposure through a shadow mask is used to align PNTs. Exposed regions become hydrophilic, leading to directed spreading of the FF solution and alignment of the PNTs that improves as the difference in wettability between adjacent regions increases, suggestion that the difference in wettability between region leads to a chemical force, which drives the alignment process. Alignment is further found to depend on the concentration and temperature-dependent diameter of the PNTs formed and the size of the hydroplic area. Finally, aligned PNT decorated with silver nanoparticles are used as templates to sense an analyte molecule (TMPyP), at different concentrations using surface enhanced Raman spectroscopy. Using aligned PNTs as template for SERS-active materials may provide route to improving the reproducibility of the SERS signal by tailoring the density and location of the materials, and may enable single molecule detections.

M.P.1
18:00
Authors : Jaeho Choi, Ilsub Chung
Affiliations : College of Information and Communication Engineering, Sungkyunkwan University

Resume : SiO2/ZrO2 asymmetric dual layered tunnel oxide was fabricated, and examined in terms of its program/erase characteristics. A lower program voltage for the target Vth indicates a faster programming benefit, which was attributed to the reduced F-N tunneling barrier due to the insertion of ZrO2. The retention behaviors of the hybrid tunnel oxides were also investigated by comparing the Vth obtained before baking with that obtained after baking at 125C. Among the combinations in thickness between SiO2 and ZrO2, the hybrid oxide having thin SiO2 combination (3 nm) yields poor retention property compared with that having thick SiO2 combination (4 nm). Such degradation in retention property was understood in terms of diffusion of Zr into SiO2 during the subsequent heat budget. The diffusion of Zr in SiO2 brings up a trade-off between the benefits of the program and erase speed and the disbenefit of the degradation in retention characteristics. That is, it increases the program and erase speed, while it deteriorates the retention characteristic. Thus, a hybrid tunnel oxide combination with relatively thick SiO2 reveals better retention behavior compared to those of reference samples. In addition, the trap density of ZrO2 was obtained by ISPP test. The result obtained from ISPP test indicates that ZrO2 in the hybrid tunnel oxide serves as a tunneling dielectric without effect on the charge storage.

M.P.2
18:00
Authors : Kunmo Koo, Sung-Wook Nam, Seung Hyeon Ko, Bonkeup Koo, Jeong Yong Lee, Jong Min Yuk
Affiliations : Center for Nanomaterials and Chemical Reactions, Institute for Basic Science; Department of Materials Science and Engineering, KAIST; Department of Molecular Medicine, School of Medicine, Kyungpook National University; Department of Materials Science and Engineering, Hanbat National University;

Resume : Observation of liquid-containing materials in transmission electron microscope is now very common analytic methodology for material scientists. Among the methods, trapping liquid between micro-fabricated silicon nitride windows, is more preferred method since it is consistent, versatile, and easy to prepare, compared to graphene liquid cells. Many vendors and research groups has developed and commercialized their liquid chip with noble structure, optimized to their research targets. Silicon nitride window liquid cell technique has many advantages, but there are also many restrictions, such as resolution degradation from liquid thickening and limitation in selection of solution due to the wettability to membrane. Introducing various metal mesh or grating pattern to nitride membrane, is shown to affect bulging effect in vacuum and wettability of membrane. Also, isolating each cell with patterned metal grating prevents solution vaporization from electron beam induced radiolysis effect.

M.P.3
18:00
Authors : Chang-Soo Lee*, Jongyeon Kim, Jungsik Ha, Youngsu Cho, Dohyung Kim, and Kangsu Kim.
Affiliations : Samsung Electronics Co., Ltd.

Resume : Copper (Cu) has been considered as an alternative material of Al for an interconnect metallization in modern ULSI devices due to its low resistivity and good electro-migration resistance. In our current devices such as dynamic random access memory and flash memory, Cu also has been widely used as a metal line at the back end of line process. Cu film was deposited on the damascene pattern by well-known electro-plating method. It was filled conformally in the trench pattern and shows favorable resistivity for the device performance. However, Cu hillocks were observed at the wafer edge area which is the range from 140mm to 150mm, and it showed slightly lower device yield in the same area. Because the generation of metal hillocks usually occurred by the compressive stress induced by the thermal budget which applied to the wafers, and we observed that the Cu hillocks were significantly decreased by the treatments to evacuate the residual Fluorine (F) from the chamber using the F reducing gases such as SiH4 and NH3, we modified the in-situ cleaning process to minimized the contact of the wafers to the heater and the residual F to suppress the Cu hillocks. In this paper, we focused the thermal budget and the F which can affect to the wafers during the in-situ cleaning process as main causes of the Cu hillocks. Thus, the modifications of the purge steps and the addition of the F removal steps using SiH4 and NH3 gases in the in-situ cleaning process were conducted to minimize the thermal budget and to remove the effect of F on the formation of Cu hillocks. Using the above methods, the formation of Cu hillocks significantly reduced from around 3600ea to 230ea (93.4% decrease). To date, because the F effect on the Cu hillock formation has rarely been studied, the mechanism for proving the F effect is proposed and discussed.

M.P.4
18:00
Authors : Seung-Wook Lee (1,2), Byung-Hyun Lee (3), and Yang-Kyu Choi (1)
Affiliations : (1) School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 34141, Republic of Korea. (2) System LSI Division, Samsung Electronics, Yongin-City, Gyeonggi-Do, 17113, Republic of Korea. (3) Memory Division, Samsung Electronics, Hwasung-City, Gyeonggi-Do, 18448, Republic of Korea.

Resume : A vertically multiple stacked nanowire FET (VMS-NWFET) has been considered as a promising candidate for the suppression of short-channel effects, high performance, and ultimate scalability [1]. A junctionless-mode (JM) VMS-NWFET has also been presented due to its reduced variability and simple fabrication process [2]. In addition, the JM VMS-NWFET showed a more suppressed low-frequency noise level than an inversion-mode (IM) VMS-NWFET due to its inherent bulk conduction [3]. As pixel sizes are scaled down, CMOS image sensor (CIS) demands improved robustness against temporal noise such as flicker noise and random telegraph signals. Accordingly, the JM VMS-NWFET is expected to be used as a source follower (SF) for CIS. In this work, the linearity of the SF gain, an important characteristic to avoid distortion of a color image, was measured and compared in the JM VMS-NWFET and the IM VMS-NWFET. It was found that the linearity of the SF gain in the JM VMS-NWFET is superior to that in the IM VMS-NWFET according to the applied gate voltage (VG) as the trap-related noise is lowered by bulk conduction in the JM. Furthermore, the improvement in the linearity of the SF gain is greater with high channel doping in the JM VMS-NWFET. However, optimization of the doping concentration is necessary because an adverse drop in the threshold voltage can occur when the doping concentration is too high. [1] B.-H. Lee et al., Nano Lett., vol. 15, no. 12, pp. 8056–8061, 2015. [2] B.-H. Lee et al., Nano Lett., vol. 16, no. 3, pp. 1840–1847, 2016. [3] T. Bang et al., IEEE EDL, vol. 38, no. 1, pp. 40–43, 2017.

M.P.5
18:00
Authors : S. Prucnal1; L. Augel2; J. Schulze2; I. A. Fischer 2; Y. Berencén1; R. Hübner1; R. Böttger1; L. Rebohle1; W. Skorupa1; M. Wang1; M. Voelskow1; M. Helm1; S. Zhou1
Affiliations : 1. Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum Dresden-Rossendorf, 01314 Dresden, Germany 2, Institute of Semiconductor Engineering, University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany

Resume : GeSn with quasi-direct band gap is one of the most promising semiconductor materials for light emitters integrated with CMOS technology. The equilibrium solid solubility limit (SSL) of Sn in Ge is in the range of 0.5 % and the predicted theoretical Sn concentration needed for the direct band gap formation is above 5 %. This means that GeSn with direct band gap is metastable and any related material process cannot be thermal equilibrium. Here we propose to utilize strongly non-equilibrium processing i.e. ion implantation followed by millisecond range flash lamp annealing (FLA), for doping and the formation of Ohmic contacts with low contact resistance on Ge0.95Sn0.05. The effective carrier concentration in P+ implanted Ge0.95Sn0.05 layer followed by FLA for 3 ms is above 5×10^19cm-3 with a specific contact resistance rc=4×10^-6Ωcm2. NiGe for Ohmic contact is made by Ni diffusion into GeSn during a single 3 ms long flash pulse. TEM images reveal that NiGe is polycrystalline but with an atomically sharp interface between the metal contact and GeSn. The influence of non-equilibrium processing (ion implantation and FLA) on the optical, electrical and microstructural properties of the GeSn layer grown by MBE on Si will be discussed in details.

M.P.7
18:00
Authors : Cheng Li, Ningli Chen, Lu Zhang, Guangyang Lin, Yisheng Wang
Affiliations : Department of Physics, OSED, Semiconductor Photonics Research Center, Xiamen University, Xiamen, Fujian 361005, People’s Republic of China

Resume : An approach to form polycrystalline GeSn thin films with high Sn composition and large size grains by depositing Sn/Ge in cycles at low temperature was proposed. Initially, Sn self-assembled islands was grown on insulating substrate, which induces in-situ sputtered Ge to crystallization to form GeSn nanocrystalline thin films with high Sn composition. Thick GeSn crystalline films were then achieved by circularly deposition of Sn/Ge layers at low temperature. The grain size of GeSn with Sn content of 15% formed after stacking 20 periods of Sn(5nm)/Ge(10nm) layers reaches about 1μm. The hole mobility of polycrystalline GeSn thin films up to 24.9cm2•V-1•s-1 is achieved with process temperature of less than 450oC. The cutoff wavelength in the response spectrum extends to 2000nm for the polycrystalline GeSn photoconductors. Those results suggest that polycrystalline GeSn films are promising for high performance thin film transistors and short wave infrared photodetector arrays on insulating substrate.

M.P.8
18:00
Authors : Yong Tae Kim1, Minho Choi2, Young Min Jhon3, and Jinho Ahn2
Affiliations : 1Semiconductor Materials and Device Laboratory, Korea Institute of Science and Technology, Seoul 02792, Korea. 2 Department of Materials Science and Engineering, Hanyang University, Seoul 04763, Korea. 3Sensor System Research Center, Korea Institute of Science and Technology, Seoul 02792, Korea.

Resume : Recently, chalcogenide materials is expected to use for neuromorphic devices due to possibilities of multi resistance levels, high speed, long retention, and low power consumption. However, it is still not reported how to improve its benefits of high speed and low power consumption since the conventional Te-based chalcogenide has serious limitation in the multi-level, high speed switching and low power consumption performances for the synaptic neural network. In this work, we have found that doped chalcogenide materials, for example, Bi doped In3SbTe2 (Bi-IST) has multi-level transition at relatively lower temperatures, the lower activation energy, the fast switching performance. Fabricating neuromorphic devices with doped chalcogenide, we have investigated that the depression and potentiation process are connected to the set operation and reset operation, respectively, and discussed the relationship among the fast phase transition, multi-synaptic signals for neuromorphic system and multi-bit memory as well as the low power operations of long-term potentiation (LTP) and long-term depression (LTD) with STDP rule.

M.P.9
18:00
Authors : Young Min Jhon1, Seong Il Kim2, and Yong Tae Kim2
Affiliations : 1Sensor System Research Center, Korea Institute of Science and Technology Seoul, Korea 2Semiconductor Materials & Devices Lab., Korea Institute of Science and Technology Seoul, Korea

Resume : Cu through silicon vias (TSVs) still requires some challenging issues related with smooth Cu seed layer and strong adhesive diffusion barrier to preventing defects due to Cu diffusion and chemo-mechanical polishing. In this work, we have suggested atomic layer deposited (ALD) WCN thin films as a promising diffusion barrier for Cu TSVs. For the deep TSV with high aspect ratio of 30:1 and 20nm diameter, step coverage of ALD-WCN is comparable with carbon nanotube (CNT) and Contact resistance of Cu/WCN/Si TSVs has as low as 9-10 Ω/contact. It’s thermal stability was measured after 700˚C for 30 min. 90% of Cu/WCN/Si TSVs are maintained within the 10% deviation from the initial value. In contrast, Cu/TiN/Si, Cu/TaN/Si, and Cu/WN/Si TSVs shows severe deviation after the same annealing conditions. Mean time to failure was also investigated with 4 different TSVs. As a result, 85 % of the Cu/WCN/Si interconnect lines are not failed till over 106 s, which means that the life time of the Cu/WCN/Si is longer than those of other interconnect lines by one order of magnitude. Furthermore, after CMP process, the defect density is almost zero in the case of WCN diffusion barrier. The excellent performance of the WCN diffusion barrier seems to be originated by the compressive film stress and strong adhesion with silicon side wall.

M.P.10
18:00
Authors : Chang Soo Kim(a,*), Seungwoo Song(a), In Young Jung(a), Min hyuk Choi(a), Sang Jun Lee(b), and Ki-Hong Kim(c)
Affiliations : (a) Division of Industrial Metrology, Korea Research Institute of Standards and Science (KRISS), Daejeon 34113, Republic of Korea; (b) Division of Convergence Technology, KRISS, Daejeon 34113, Republic of Korea; (c) AE Group, Platform Technology Lab., SAIT, Samsung Electronics Co. Ltd., Suwon, 16678, Republic of Korea

Resume : In CMOS devices of sub-0.1 um regime, the thickness of SiO2 gate oxide is less than 1.5 nm, where the leakage current rises to an unacceptable limit. One of the alternative is to replace SiO2 with a material with higher dielectric constant, and HfO2 is one of the most promising high-k materials. Ultra-thin HfO2 films of 3.5, 5.0, and 8.0 nm were prepared, respectively, on silicon substrates by using ALD method. Through the analyses of XRR, XPS and TEM for HfO2 films with or without surface cleaning, surface contamination layer was identified and the thickness of surface contamination layer were measured. X-Ray specular reflectivity at a particular incidence angle increased after the cleaning of the sample, and decreased again to a similar value to the reflectivity of as-received sample after being exposed to atmosphere for two weeks. XPS results showed that the changes in reflectivity due to the cleaning were caused by varying amount of surface contamination of the sample. XRR curves changed and the positions of thickness fringes were different for the identical sample with or without the surface cleaning, and the thicknesses determined from Fourier analyses of the XRR curves were different due to different surface contamination. Fourier analysis of the XRR curve measured by synchrotron source revealed the existence of a surface contamination layer of about 1 nm thickness. Simulation for XRR curve showed the best fit to data when contamination layer of about 1 nm thickness was considered, and the result was consistent with that of the Fourier analysis. Finally, a surface contamination layer was identified, and the thickness of the contamination layer as well as the thicknesses of HfO2 films were determined precisely.

M.P.11
18:00
Authors : Inho Kim, Kyung Won Seo
Affiliations : Department of Chemical Engineering, Ajou University; R&&D Center, Hansol Unitimate Inc.

Resume : Our development focused on metal oxide chemiresistive gas sensor using TiO2, and we have fabricated platform including Pt microheater heater and interdigitated electrode (IDE) by micro-electro-mechanical system (MEMS) processes. Specified Pd decorated TiO2 thin film have been mounted on the top of the IDE by radio-frequency (RF) sputtering with 300 W of RF power and gas sensing performances have been investigated for hydrogen gas detection. The gas sensor with 200 nm TiO2 thin film under 200 °C of operating temperature showed higher sensitivity with less than 50 mW power consumption. The microstructures of material were systemically characterized by FESEM, AFM and X-ray diffraction patterns and we also discussed the effect of microstructure to gas sensing properties.

M.P.12
18:00
Authors : Mantas Norkus, Mindaugas Kamarauskas*, Audru?is Mironas, Saulius Balakauskas, Virginijus Bukauskas, Marius Treideris, Ar?nas ?etkus (*presenting author)
Affiliations : Center for Physical Sciences and Technology, Sauletekio ave. 3, LT-10257 Vilnius Lithuania

Resume : Rapidly expanding interests in the technology of the two-dimensional (2D) materials are stimulated by highly promising advantages demonstrated for development of electronic devices based a monolayer of a 2D-material. Low power consumption, unique characteristics and nanoscaling of the devices are the most attractive features for practical applications. It is already known that depending on the number of monolayers, the band gap of the MoS2 can be modified and a variation of parameters with spectrum can be intentionally modified by the number of MoS2 monolayers in the photonic devices. In this work we developed an original technological method to synthesize a predictable number of the MoS2 monolayers by intentional control of the metallic Mo precursor. MoS2 films were prepared by sulfurization of Mo layers deposited on the substrate. As synthesized structures were characterized by AFM and Raman scattering measurements. Technological deposition and sulfurization parameter influence on the properties of the MoS2 films were investigated. We demonstrate that intentionally changing deposited Mo film thickness from < 1 nm to 4 nm we can change the number of monolayers, after sulfurization, in the resulting MoS2 films from 1 to ?4.

M.P.13
18:00
Authors : Vera Murza1, Leonid Vradman2,3, Yuval Golan1,4
Affiliations : 1Department of Energy Engineering, Ben-Gurion University of the Negev, Beer-Sheva 84105, Israel 2Department of Chemistry, Nuclear Research Centre Negev, Beer-Sheva 84190, Israel 3Department of Chemical Engineering, Ben-Gurion University of the Negev, Beer-Sheva 84105, Israel 4Department of Materials Engineering, and the Ilse Katz Institute for Nanoscale Science and Technology, Ben-Gurion University of the Negev, Beer-Sheva 84105, Israel

Resume : Chemical Bath Deposition (CBD) is a simple and inexpensive technique for thin film deposition of a variety of semiconductors upon substrates such as silicon and gallium arsenide. Nevertheless, this technique experiences some drawbacks such as change of reactant concentrations and spatial non-uniformity. Liquid flow deposition (LFD) is a variation of CBD with potentially improved performance. In the current research LFD was studied using a custom made reactor. The deposition of lead sulfide (PbS) on gallium arsenide (GaAs) substrate was explored as a test case. PbS is widely studied for different applications such as photovoltaic cells, IR detectors and thermoelectric devices. The main objectives of the current research were to enhance understanding of thin film deposition by comparing the LFD and CBD methods, and optimization of PbS thin film deposition using LFD. High Resolution Scanning Electron Microscopy (HR-SEM) and X-ray Diffraction (XRD) revealed films with <110> oriented crystals with ~800 nm grain size for both methods. There were much less particles precipitating on the film surface in the case of LFD compared to CBD. The initial growth rate of PbS films via LFD was found to be lower than in CBD, resulting in thinner film thickness and suggesting that LFD is more suitable for growing films via the ion-by-ion mechanism. Kinetic studies show that the maximal growth rate in the reactor was achieved when residence time corresponded to half of the induction time. Moreover, as expected, the growth rate in LFD reactor increases with time up to 60 nm/min after 2 hours of deposition, while in CBD the growth rate drops after half an hour of deposition.

M.P.14
18:00
Authors : Seon Yong Hwang1, Woong Sun Lim1, Won Myoung Choi1, Hyun-Beom Shin1, Hyeong-Ho Park2, Sang Hyun Jung2
Affiliations : 1 Convergence Technology Division, Korea Advanced Nano Fab Center; 2 Device Technology Division, Korea Advanced Nano Fab Center

Resume : Wafer to wafer bonding was studied for wafer level packaging of various high integrated and multi-dimensional sensors. These wafer to wafer bonds were performed at low temperatures under 450 °C and involved either field-assisted silicon to glass anodic bonding or a eutectic bond between wafers using a gold (Au) and other metals. And, it is essential to study that low temperature bonding for heterogeneous wafers, because the higher temperature bonding may induce cracks, defects, bowing, and destruction by different thermal expansion coefficients of the heterogeneous wafers. We investigate low process temperature eutectic bonding with Au-indium (In) metal alloy for the application of III-V compound semiconductor based magnet sensor devices on silicon wafer. The bonding temperatures of Au-In is 210 °C, respectively. The indium layer melts and dissolves the Au layer to form a mixture of liquid and solid. A field emission scanning electron microscopy (FE-SEM) was used to determine the excellent bonding quality of the interface of wafer to wafer bonding. An energy-dispersive X-ray spectroscopy (EDS) was employed to determine the composition of the resulting Au-In wafer to wafer bonds. The resulting bonds have de-bonding temperature of Au-In greater than 450 °C, respectively. The bonding strength of Au-In wafer to wafer bonding is 13.4 MPa. Due to the low process temperature, the stress on the bonded structure caused by thermal expansion mismatch is reduced.

M.P.16
18:00
Authors : Hae Yong Jeong, Hyeong-Ho Park, Jin-Seok Jeon, Kyung-Ho Park
Affiliations : Electronic device Lab., Korea Advanced Nano fab Center, Suwon 16229, Republic of Korea

Resume : Various fabrication technologies for atomic force microscopy (AFM) probes have been investigated, emphasizing the fabrication of high-aspect-ratio silicon tip, which can be integrated with micromachining techniques. Currently, most AFM probes are formed directly by anisotropically wet etching. In this work, proposed processes for making sharp silicon tip are classified into three categories; (1) anisotropic etching of silicon using various concentrations of KOH solution; (2) self-sharpening technique for anisotropically wet etching, which is used etch mask aligned to <310> directions; and (3) combined anisotropic etching with isotropic etching of silicon using various compositions of nitric acid, water, and hydrofluoric acid. Sharp silicon tips were achieved using a matrix of etching conditions, and results were analyzed using a scanning electron microscope(SEM). Both the tips and cantilevers are simultaneously formed by a masked-maskless combined anisotropic etching process. As a result, novel high-aspect-ratio silicon tip shapes have been achieved and integrated with AFM cantilevers. A simple and high yield method for the fabrication of cantilever with a high-aspect-ratio silicon tip will be presented in the conference.

M.P.17
18:00
Authors : E. Schapmans(a), C. Merckling(a) (a) imec (b) Aixtron
Affiliations : F. Buttitta(b), M. Kelman(b) (a) imec (b) Aixtron

Resume : The growth of a high quality epitaxial layer requires a clean initial substrate surface. In the difficult case of hetero-epitaxy on Si, optimization of the pre-epi clean sequence focuses on surface preparation and efficient Si de-oxidation. The classical combination of a HF wet etching followed by high temperature H2 bake (> 950C) sequence will efficiently de-oxidized the Si surface with perfect step and terraces surface morphology. However the implementation of this pre-epi clean sequence in a CMOS integration scheme is limited due to integration driven thermal budget constraints leading to reflow and/or relaxation of effects. In that context, we are studying the use of an in-situ pre-epitaxy clean in combination with a low thermal H2 bake budget (< 650C) for III-V hetero-epitaxy on Si as an alternative to the standard procedure for Si surface preparation. We developed an in-situ dry etch approach consisting of fluorine based chemistry as an alternative option. We will benchmark the different options (wet-etch versus dry etch, with and without high temperature H2 bake) and characterize them on blanket Si substrates in terms of Si selectivity, Si surface roughness and residual contaminations (O, F, C, ...) after in-situ dry etch process. In a final part, we will study the impact of the fluorine based in-situ dry etch process on Si/SiO2 patterned substrate prior to III-V selective area epitaxy.

M.P.18
18:00
Authors : Donghwan Lim, Hoon Hee Han, and Changhwan Choi
Affiliations : Division of Materials Science and Engineering, Hanyang University, Seoul 04763, Korea

Resume : Tunneling field-effect-transistor (TFET) has been strongly investigated as a promising candidate device for the low power application due to steeper subthreshold swing, low off current and its scalability. However, it has still several challenges since TFET needs abrupt junction between source and channel as well as requires low-doped substrate in the form of p-i-n structure. Particularly, modulating symmetric threshold voltage (Vth) for the realization of CMOS inverters is of great interest. Controlling gate electrode’s work-function is the way to tune Vth of SOI-like TFETs. In this study, all ALD gate stack (HfAlOx/TiN) was used, where ALD TiN thickness was varied to modulate Vth in n- and p-MOS TFETs, and bias temperature instability against the electrical stress was compared. We fabricated the gate-last like TFET on the 6-inch p-type SOI substrate. After thinning SOI to 50 nm by oxidation, wet etching and active formation steps were followed. To mimic gate last process, BF2 and As were implanted (10 keV, 3.0×1014 cm-2) into the source and drain region, respectively, followed by dopant activation annealing at 950 ˚C for 5 seconds. Gate stack with ALD HfAlOx (Al 25%, HAO) using TEMA-Hf and H2O as well as ALD TiN using TiCl4 and NH3 was employed, where ALD TiN was with thickness of 5 nm and 10 nm. To reduce the contact resistance, we added PVD TiN as a capping metal. Total thickness was kept to 150 nm. The subsequent processes followed the conventional transistor processes. As a reference, both MOSFET and TFET with PVD TiN of 150 nm thickness were fabricated as well.Compared to PVD TiN, ALD TiN enhances Vth and its impact is increased further with thicker TiN for both MOSFET and TFETs. In TFETs ALD TiN of thickness of 5 nm and 10 nm induces 60 mV and 120 mV shift of Vth, respectively, in n-TFET while 5 nm-thick ALD TiN and 10 nm-thick ALD TiN of p-TFET leads to 90 mV and 170 mV shift, respectively, compared to PVD TiN-based n-TFET and p-TFET. The extracted interface traps state (Nit) values from Icp measurement are ~7.2x1011 cm-2, ~6.0x1011 cm-2, and ~8.5x1011cm-2 for ALD 5nm-thick TFET, ALD 10 nm-thick TFET, and reference PVD TiN TFET, respectively, proving that ALD TiN is superior to PVD TiN in terms of the electrical Vth stability due to the absence of plasm-induced damage. To obtain the Vth modulation knob for the realization of CMOS TFETs, we demonstrated low temperature ALD TiN gated TFETs with Vth tunability by varying TiN thickness. Compared with PVD TiN, adding ALD TiN into gate electrode leads to Vth shift up to 170 mV as well as lower Nit generation against the electrical stress. Our results provide the feasibility of Vth modulation of TFET with ALD TiN thickness variation. [Acknowledgement]: This work was supported by the Future Semiconductor Device Technology Development Program (10044842) funded By MOTIE (Ministry of Trade, Industry & Energy) and KSRC (Korea Semiconductor Research Consortium).

M.P.19
18:00
Authors : T. Haffner1, F. Bassani1, M. Zeghouane1, S. David1, P. Gentile2, A. Gassenq2, N. Pauc2, E. Martinez3, T. Baron1, B. Salem1
Affiliations : 1 Univ. Grenoble Alpes, LTM, F-38000 Grenoble, France CNRS, LTM, F-38000 Grenoble, France 2 Univ. Grenoble Alpes, F-38000 Grenoble, France SiNaPS, CEA, INAC, F-38054 Grenoble, France 3 Univ. Grenoble Alpes, F-38000 Grenoble, France CEA-LETI, MINATEC Campus, F-38054 Grenoble, France

Resume : GeSn group-IV material is experiencing a renewed interest partly due to the recent demonstration of laser emission from GeSn layers grown on Ge/Si(001)-virtual substrates. It has been predicted an indirect-to-direct transition for unstrained GeSn alloys with Sn concentrations in the range from 6 to 12%. However, two major issues have to be overcome to obtain high cristalline quality GeSn layers which are mainly the low equilibrium solubilty (<1%) of Sn in Ge and the large lattice mismatch (~15%) between Ge and -Sn. NWs could offer the possibility to grow high cristalline quality GeSn material thanks to the strain relaxation on the large specific surface developed. In this work, we have investigated Sn incorporation in Ge NWs grown by chemical vapor deposition (CVD) via the vapor-liquid-solid mechanism (VLS). This growth process is a non-equilibrium one which should facilitate the incorporation of Sn into the Ge NWs. In our experiments, GeH4 and SnCl4 were used as gas precursors. Several growth conditions such as the growth temperature, the SnCl4/GeH4 ratio, and the total pressure in the reactor were varied in order to determine the best growth conditions for incorporating a maximum of Sn in the Ge NWs. Sn concentrations in the Au catalysts were measured using EDX and radial Sn distribution in Ge NWs was obtained by Auger profiling and/or STEM-EDX measurements. The obtained results will be presented.

M.P.20
18:00
Authors : E.Martín 1, J. Schlipf 2, I. A. Fischer 2, J. Schulze 2, S. Chiussi 3
Affiliations : 1 Dpto. Mecánica, Máquinas, Motores Térmicos y Fluidos, Univ. de Vigo, Campus Universitario, 36310 Vigo, Spain; 2 Institut für Halbleitertechnik (IHT), Universität Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany; 3 Dpto. Física Aplicada, Univ. de Vigo, Rua Maxwell s/n, Campus Universitario Lagoas Marcosende, 36310 Vigo, Spain

Resume : A theoretical approach to predict temperature gradients during Pulsed Laser Induced Epitaxy (PLIE) of SiGe alloys with SiO2 hard masks is proposed and obtained results are compared with experimental ones. PLIE is based on laser induced fast melting/solidification processes that allows fast processing and in-situ monitoring of growing SiGe based alloys. Predicting the layer structure and the energy densities as well as number of laser pulses, needed for the successful growth of high quality SiGe based alloys is essential for its use in the fabrication of future integrated laser devices. A deeper understanding of the growth process is required and a theoretical approach has therefore been followed, using Finite Element Methods (FEM). Simulations were carried out with Software Comsol, by evaluating a one dimensional unsteady melting-solidification thermal problem, using the effective specific heat technique, coupled to a set of unsteady convection diffusion equations (activated during the melting process) of the different involved layers. Different scenarios were considered: firstly, the analysis of a 200nm Ge layer over the Si(100) wafer for two values of applied laser fluences (0.3 and 0.7 J/cm^2) up to 50 laser pulses. Comparison of melting times and concentrations distributions between the numerical results and the experimental ones served to validate the mathematical model and the used parameters. Secondly, 1D numerical simulations of SiO2 hardmask with different thicknesses over the previous layout were considered in order to quantify the optimal thickness to prevent melting of the hard mask. The model developed in this work will be applied in future over 3D problems making the design and selection of suitable masks easier.

M.P.21
18:00
Authors : M.Merhej1,2,3,4 ,T. Honegger1,2, S. Ecoffey3,4, F. Bassani1,2, T. Baron1,2, D. Peyrade1,2, D. Drouin3,4 and B. Salem1,2
Affiliations : 1- Univ. Grenoble Alpes, LTM, F-38000 Grenoble, France. 2- CNRS, LTM, F-38000 Grenoble, France. 3- Laboratoire Nanotechnologies Nanosystèmes (LN2) - CNRS UMI-3463, Université de Sherbrooke, 3000 Boul. Université, Sherbrooke, J1K 0A5, Qc, Canada. 4- Institut Interdisciplinaire d'Innovation Technologique (3IT), Université de Sherbrooke, 3000 Boul. Université, Sherbrooke, J1K 0A5, Qc, Canada.

Resume : Nanowires (NWs) are emerging building blocks for the bottom–up assembly of nanodevices and functional systems, holding promise for a variety of field applications including chemical and biological sensors, field effect transistors, light-emitting diodes, optoelectronics, and photodetectors. There have been extensive studies on their synthesis, with considerable advances made in the control of the structure, electrical, and thermal properties. Silicon and silicon-germanium nanowires (SiNWs/SiGeNWs) appear particularly important because of their potential applications in microelectronics areas and their ability to perform band-engineering in order to improve carrier’s mobility nanowires. However, placement of nanowires and post growth manipulation in a coherent and useful way continues to be a considerable challenge. In this context we will present two complementary strategies to localize precisely the Si and SiGe nanowires on CMOS chip. (i) First, using dielectrophoresis technique and second, (ii) direct growth of NW assembly on pre-patterned electrodes using Vapor-liquid-solid (VLS) mechanism.

M.P.22
18:00
Authors : Clement Porret*,1, Srinivasan Ashwyn Srinivasan1,2,3, Daire Cott1, Rajrupa Paul1, Sakshi Anand1, Marianna Pantouvaki1, Dries Van Thourhout1,2,3, Joris Van Campenhout1 and Roger Loo1
Affiliations : 1 imec vzw, Kapeldreef 75, 3001 Leuven, Belgium 2 Photonics Research Group (INTEC), Ghent University-imec, Ghent, Belgium 3 Center for Nano- and Biophotonics (NB-Photonics), Ghent University, Ghent, Belgium

Resume : The need for high-bandwidth interconnects with reduced power consumption is becoming critical with the advent of cloud computing. The integration of Si photonics on CMOS platforms is the subject of intensive developments. Ge-based electro-optical modules, such as integrated light sources, variable optical attenuators, photodetectors and modulators, receive a lot of attention owing to their compatibility with Si and promising performance. Epitaxial Ge, grown on Si, plays a key role in the fabrication of these devices. However, Ge/Si heterostructures typically suffer from high threading dislocation and interface trap densities, which degrade the final performance (Chen et al., JAP, 119, 213105 (2016)). Here, the post Ge epitaxy thermal treatment is adjusted to demonstrate free-carrier lifetimes as high as 7ns in 1µm-thick Ge virtual substrates. In addition, we compare different schemes for the passivation of polished, 600nm-thick, Ge layers having a controlled threading dislocation density of 6E7cm-3. Time-resolved photoluminescence measurements allow for the extraction of surface recombination velocities, taking into account the Ge/Si interface recombination velocity as determined by Srinivasan et al. (APL, 108, 211101 (2016)). The use of either an epitaxially grown Si cap or GeO2 based passivation approach allows a significant increase in carrier lifetime in Ge, with respect to unpassivated Ge and to Ge capped with SiO2 as standardly used for device isolation.

M.P.23
18:00
Authors : Kudryashov Dmitry, Gudovskikh Alexander
Affiliations : St. Petersburg National Research Academic University RAS

Resume : Gallium phosphide with a small amount of nitrogen and arsenic is a promising material for silicon based integration due to its lattice parameters and a wide range of band gaps (1.5 - 2.0 eV) [1]. It is still a serious challenge to grow a high quality GaP(NAs) layers on silicon but multijunction solar cells [2] and light emitting diodes [3] were already fabricated. Parameters of semiconductor devices are also depend on post-growth processing steps such lithography and etching. Precise etch depth control is needed for example to separate study of layers properties in device structure and also for a contacts fabrication. Dry etching is the most widely used processes in industry and research but a probability of active layer degradation due to high energy particles exists. This paper presents some results concerning wet etching of GaP(NAs) layers grown by MBE on silicon wafer. As a result, structures for direct measuring of sub-cells characteristics in GaP(NAs)-based dual-junction solar cell were made. The I-V and CV-curves for top and bottom sub-cells were successfully measured. This work is supported by the Russian science foundation, grant RSCF, project No 17-19-01482 [1] J. F. Geisz, D. J. Friedman, and S. R. Kurtz, in Proceedings of the 29th IEEE PVSC (New Orleans, LA,2002), p. 864. [2] A.S. Gudovskikh et al. Proc. 29th EU PVSEC 2014 Amsterdam Netherlands 2014 4CV.3.3 [3] A. V. Babichev et al. Semiconductors (2014) V. 48. pp 501–504

M.P.24
18:00
Authors : El-Asaad Chebaki 1, Fayçal Djeffal 1,2,* and Toufik Bentrcia2
Affiliations : El-Asaad Chebaki 1, Fayçal Djeffal 1,2,* and Toufik Bentrcia2 2 LEA, Department of Electronics, University of Batna 2, Batna 05000, Algeria. 1 LEPCM, Department of Physics, University of Batna 1, Batna 05000, Algeria. *E-mail: faycal.djeffal@univ-batna.dz, faycaldzdz@hotmail.com, Tel/Fax: 0021333805494

Resume : In recent years, the investigation of Multi-gate Metal Oxide Semiconductor Field Effect Transistors (MG MOSFET) has attracted more attention due to their high electrical performance and scalability provided for nanoelectronic applications. In this context, to analyze the Junctionless Gate All Around (JL GAA) MOSFETs is a challenge because the parasitic phenomena appearing at deep submicron level, where the short channel and ageing effects are considered the critical negative aspects that need to be investigated carefully. Up to our knowledge, no investigations have been carried out considering both electrical performance and device degradation-related ageing effects. In this context, in this work we present a numerical investigation of junctionless GAA MOSFET including degradation-related ageing effects to study the nanoscale JLGAA MOSFET Reliability against the ageing phenomenon. Moreover, the effect of the stress time and channel length on the device performance is presented. In order to show the impact of the proposed approach on the electronics circuits designing, the developed model has been implemented to study the performance behavior of voltage amplifier circuit including degradation-related ageing effects. Therefore, the proposed approach can offer new insights regarding the investigation and simulation of the nanoelectronic circuits including the degradation-related ageing effects.

M.P.25
18:00
Authors : K.S. Zelentsov, A.V. Uvarov, I.A. Morozov and A.S. Gudovskikh
Affiliations : Saint-Petersburg Academic University, Hlopina str. 8/3, St.-Petersburg, Russia

Resume : Lattice-matched systems of III-V compounds grown on Si substrates are very promising for optoelectronic and photovoltaic application. The efficiency of III-V/Si multijunction solar cells could exceed 50%. GaP provides better charge carrier mobilities and higher bandgap value (2.26 eV) compared to that of a-Si:H. This results in GaP/Si heterojunction being advantageous for high-efficient solar cells. According to numeric simulation, electrical properties of GaP/Si heterostructures depend on whether Ga-Si or P-Si bonds are formed. However, epitaxial growth of GaP requires high temperatures (> 600°C) which lead to interface blurring and the formation of both types of bonds at the same time. In this work, we present our results in growing GaP/Si structures on (100) Si substrates by low-temperature PE-ALD method. The growing process is tuned to start with Ga or P atoms. The influence of abrupt Ga-Si and P-Si interface on band bending and band offset will be studied by capacitance measurement techniques.

M.P.26
18:00
Authors : B. Zerroumda1, F. Djeffal 1,2,*, T. Bentrcia2 and H.Ferhati1
Affiliations : 1 LEA, Department of Electronics, University of Batna 2, Batna 05000, Algeria. 2 LEPCM, Department of Physics, University of Batna 1, Batna 05000, Algeria. *E-mail: faycal.djeffal@univ-batna.dz, faycaldzdz@hotmail.com, Tel/Fax: 0021333805494

Resume : In recent years, Vertical 4H-SiC Power MOSFETs exhibit superior performance relative to lateral MOSFETs due to the higher carrier mobility in the c-plane 4H–SiC, high break-down electric field and high thermal conductivity. However, these devices suffer from low values of the channel mobility in the inversion layer due to the high interface state density (DIT) near the SiC/SiO2 interface, which leads to the degradation of the device Figures of Merit such as: on-resistance, break-down voltage and the derived current. The main objective of this work is to investigate the reliability performance of Vertical 4H-SiC Power MOSFET device including interface state density effects. Up to our knowledge, few investigations have been carried out considering both electrical performance and device degradation-related interface traps effects. In this context, in this work we present a numerical investigation of Vertical 4H-SiC Power MOSFET including degradation-related interfacial defects to study the device reliability. Moreover, the effect of the channel length, oxide permittivity and cannel doping effects on the device performance is presented. The proposed approach can offer new insights regarding the investigation of the power electronic devices including the degradation-related interfacial defects.

M.P.27
18:00
Authors : W. Mortelmans1,2, S. El Kazzi1, T. Nuytten1, S. Crahaij1, J. Meersschaut1, D. Vanhaeren1, L. Landeloos1, T. Conard1, I. Hoflijk1, H. Bender1, C. Merckling1 and M. Heyns1,2
Affiliations : 1Imec, Kapeldreef 75, B-3001 Leuven, Belgium 2Department of Metallurgy and Materials Engineering, KU Leuven, Kasteelpark Arenberg 44, B-3001 Leuven, Belgium

Resume : As fundamental physical limits of Silicon-based integrated circuits are arising, novel materials such as 2D Transition Metal Dichalcogenides (TMDs) are gaining significant scientific importance. Within this perspective, 2D WSe2 monolayers are of great interest due to the unique ambipolar behavior of the semiconductor enabling both p- and n-type devices. Also, combined with other 2D materials, WSe2 shows to be the material of interest for a next generation of tunneling or low power transistors. Nonetheless, as Raman spectroscopy is considered to be a main technique for TMD characterization, careful interpretation of the Raman spectra of WSe2 monolayers is made difficult by the overlap of the main two first-order Raman active vibrational modes at ~250 cm-1. Therefore in a first stage of this work, we perform an in-depth Raman spectroscopy study on high crystalline quality WSe2 exfoliated flakes for an improved interpretation of the Raman spectra of the WSe2 monolayers grown by Gas Source Molecular Beam Epitaxy (GSMBE). In a second stage, we present that the combination of Raman spectroscopy with other physical characterization techniques (e.g. RHEED, RBS, XPS, AFM and TEM) allows a better understanding on the structural and chemical properties of the WSe2 monolayers. We demonstrate that the link between these complementary characterization techniques is very beneficial to assess material quality, and so paving the way to effective ultrathin 2D material study and learning.

M.P.28
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M-6: Heteroepitaxy and Nanoelectronics I : tba
09:00
Authors : Georgios Katsaros
Affiliations : Institute of Science and Technology Austria, Am Campus 1, 3400 Klosterneuburg, Austria

Resume : In the past 10 years many groups have used electrons confined in group IV quantum dots in order to realize spin qubits [1]. Impressive progress in the extension of spin lifetimes has been achieved and record coherence times of about 1 second were reported for 31P electrons in isotopically engineered 28Si substrates [2]. Holes on the other hand are much less studied [3]. Theory predicts that holes can show similar spin lifetimes as electrons [4] and should be promising for creating long distance two qubit gates [5]. In this talk the focus will be on holes confined in Ge self-assembled hut wires [6]. Magnetotransport measurements of three terminal devices revealed a large g-factor anisotropy originating from the heavy-hole character of the confined states [7]. Recent results of charge sensing and magnetotransport measurements of double quantum dot devices will be presented. References: [1] F. A. Zwanenburg et al., Rev. Mod. Phys. 85, 961 (2013) [2] J. T. Muhonen et al., Nature Nanotechnology 9, 986 (2014) [3] Y. Hu et al., Nat. Nanotechn. 7, 47 (2012) ; A. P. Higginbotham et al., Nano Letters 14, 3582 (2014) ; R. Maurand et al., Nature Com. 7, 13575 (2016) [4] D. V. Bulaev et al., Phys. Rev. Lett. 95, 076805 (2005) [5] S. E. Nigg et al., Phys. Rev. Lett. 118, 147701 (2017) [6] J. J. Zhang et al., Phys. Rev. Lett. 109, 085502 (2012) [7] H. Watzinger et al. Nano Letters 16, 6879 (2016)

M.6.1
09:30
Authors : Maksym Myronov
Affiliations : Department of Physics, The University of Warwick, Coventry CV4 7AL, UK

Resume : Carrier mobility is one of the most important parameters of any semiconductor material, determining its suitability for applications in a large variety of electronic devices including field effect transistors (FETs). Germanium, with its very high intrinsic hole and electron mobilities of 1900 and 3900 cm2V-1s-1 at room temperature, respectively, is the most promising candidate material to replace Si channels in future complementary metal oxide semiconductor (CMOS) devices. Adoption of Ge technology recently came closer to reality after demonstration of superior quality GeO2 gate dielectric and very high electron and hole mobilities obtained near the GeO2/Ge interface in bulk Ge metal oxide semiconductor field effect transistor (MOSFET) devices. Biaxial compressive strain further enhances the hole mobility in Ge. The strain narrows the band gap of Ge and causes the appearance of a quantum well (QW) in the valence band. Holes confined in the strained Ge QW form a two-dimensional hole gas (2DHG) and have an increased mobility due both to their lower effective mass and reduced scattering factors in this material system. During the recent years a major breakthrough have been achieved in enhancement of carrier mobility in strained epitaxial Ge grown on a standard Si(001) substrate. Extremely high room- and low-temperature 2DHG mobilities of up to 4,500 cm2V-1s-1 and 1,500,000 cm2V-1s-1, respectively, have been demonstrated. These hole mobilities are the highest not only among the group-IV Si and Ge based semiconductors, but also among p-type III–V and II–VI materials. The latest achievements reveal a huge potential for future applications of this material in a wide variety of electronic devices.

M.6.2
10:00
Authors : Isabelle Bertrand, Luciana Capello, Oleg Kononchuk isabelle.bertrand@soitec.com
Affiliations : SOITEC, Parc technologique des Fontaines, 38190 Bernin, FRANCE

Resume : In a constant need to improve linearity and insertion loss of modern smart phones front end modules, SOI wafers, with trap-rich layer and high resistivity substrate, are well adapted for RF applications. Stable, high resistive Si is required. It is known that oxygen atoms present in Cz-Si can create thermal donors and change resistivity. Less work has been done on rapid thermal annealing (RTA) effects on electrical properties. RTA on Si wafers can generate vacancy-oxygen complexes, generally studied through Pt diffusion, but no direct electrical detection has been reported in literature. In this work, we report changes in the resistivity profiles of high resistivity Si wafers after RTA measured by spreading resistance technique. SRP show donor centers generation, with concentration and depth diffusion close to so-called slow vacancy species found in literature. We studied RTA parameters impact, such as temperature, duration, ramp-down rate, subsequent annealing in the 800°C-1000°C range, and annealing ambient on carrier concentration. Mainly all the results are consistent with the behavior of vacancy-oxygen complexes reported in the literature. We also showed that generated donor concentration is directly proportional to interstitial oxygen concentration. Finally, simulations lead to apparent diffusivity fitted with the literature estimations, confirming that vacancy-oxygen complexes are responsible for the donor activity measured. Possible ways to stabilize the resistivity after RTA will be discussed.

M.6.3
10:15
Authors : E. Rosseel (a), D. Kohen (b), A. Hikavyy (a), C. Porret (a), R. Loo (a), J. Tolle (c), A. Vandooren (a), A. Veloso (a), N. Collaert (a), D. Mocuta (a), R. Langer (a)
Affiliations : (a) IMEC, Kapeldreef 75, B-3001 Leuven, Belgium (b) ASM, Kapeldreef 75, B-3001 Leuven, Belgium (c) ASM, 3440 East University Drive, Phoenix, AZ 85034, USA

Resume : As CMOS transistors are scaled down beyond the 10 nm technological node, the metal/semiconductor contact resistance becomes a dominant contributor to the total parasitic resistance of the FinFET, lateral Gate All Around or Nanowire FET. The utilization of highly-P doped Si:P for the selective source/drain epitaxy becomes a key enabler to achieve a low contact resistivity. When epitaxy is required in the presence of buried metals (like for 3D sequential integration or for the integration of vertical nanowires), there is an additional constraint to keep the thermal budget as low as possible. In this paper we focus on selective epitaxial Si:P growth at temperatures below 500ᵒC, which is defined as the highest acceptable process temperature. As the conventional combination of Dichlorosilane (DCS, SiH2Cl2) and Hydrochloric acid (HCl) gives insufficient growth rates at these temperatures, we rely on the use of Silcore (Si3H8) and cyclic-deposition-etch with chlorine (Cl2) to achieve a selective growth with sufficient growth rate. We demonstrate uniform Si:P source/drain layers with phosphorus concentrations up to 4% and a resistivity below 0.3 mOhm.cm without the need for additional post epi activation.

M.6.4
10:30 Coffee Break    
 
M-7: Heterointegration : Maksym Myronov
11:00
Authors : Jean-Noël Aqua*, Peter Voorhees, Kailang Liu, Isabelle Berbezier, Thomas David, Luc Favre, Antoine Ronda, Marco Abbarchi
Affiliations : University Paris 6, Nortwestern University, Aix-Marseille University

Resume : We evidence that the self-organization of strained quantum dots follows different pathways as dictated by the growth kinetics. They result from a stochastic nucleation at high strain, and from the Asaro-Tiller-Grinfel'd (ATG) instability at low strain. We elucidate here the kinetic origin of the crossover between these two pathways thanks to a joint theoretical and experimental work. Nucleation is described within the master equation framework. By comparing the nucleation time scale and ATG characteristic time, we show that the former exhibits a strong exponential divergence at low strain while the latter behaves only algebraically. The crossover between the nucleation and ATG instability is found to occur both experimentally and theoretically at a Ge composition around 50%.

M.7.1
11:30
Authors : S. Bietti (1), A. Ballabio (2), L. Esposito (2), A. Fedorov(3), A. Scaccabarozzi (1), A. Vinattieri (4), F. Biccari (4), M. Gurioli (4), G. Isella (2), L. Miglio (1) and S. Sanguinetti (1)
Affiliations : 1 LNESS and University of Milano-Bicocca Italy E-mail: sergio.bietti@unimib.it 2 L-NESS and Politecnico di Milano Italy 3 L-NESS and IFN-CNR Italy 4 University of Florence Italy

Resume : The integration of optoelectronic and photonic devices based on III–V semiconductors on Si-based integrated circuits is far from being optimized despite its technological relevance. Due to the differences in lattice parameters and thermal expansion coefficients, high density of defect is introduced. We propose a novel approach for the fabrication of GaAs/AlGaAs heterostructures on nominal (001) Si substrates based on suspended Ge epilayers. To eliminate dislocations and thermal cracks we use a patterned Si substrate on which we grow with a LEPECVD system, separated vertical Ge micro-crystals, efficient in eliminating the threading dislocations and the thermal strain. From such micro-crystals, a suspended Ge layer, hundreds of microns wide and free of thermal stress can be obtained. The suspended Ge shows a wavy surface on which double steps are formed, permitting the reduction of anti-phase domains even in absence of substrate tilt. GaAs layers were grown on such Ge/Si substrate in a MBE system. Different growth recipes were studied. We found that diffusion length of Ga adatom, which is related to the average nucleation distance of GaAs islands, has a crucial role in the determination of the average APD size. In the optimum growth conditions, it was possible to observe average dimensions of APD free area with a lateral dimension of 30 μm. Macro and Micro-PL of AlGaAs/GaAs QWs grew on top show that uniform, optical quality GaAs layers are fabricated.

M.7.2
11:45
Authors : Tiphaine Cerba [1,2], Mickaël Martin[1], Jeremy Moeyaert[1], Sylvain David[1], Jean-Luc Rouviere[4], Laurent Cerutti[3], Reynald Alcotte[1,2], Jean-Baptiste Rodriguez[3], Hervé Boutry[2], Franck Bassani[1], Yann Bogumilowicz[2], Eric Tournié[3], Thierry Baron[1]
Affiliations : 1 LTM-CNRS, Univ. Grenoble Alpes, 17 avenue des Martyrs, 38054 Grenoble, France 2 LETI-CEA, Univ. Grenoble Alpes, 17 avenue des Martyrs, 38054 Grenoble, France 3 IES-CNRS, Univ. Montpellier, 860 Rue St - Priest, 34090 Montpellier, France 4 INAC-CEA, Univ. Grenoble Alpes, 17 avenue des Martyrs, 38054 Grenoble, France

Resume : Antimony based semiconductors are good candidate to substitute the Si in optoelectronic and nanoelectronic applications due to their intrinsic properties: direct band gap and high mobility of carriers. In the other hand, III-V materials have to be grown directly on Si substrate in order to match with industrial specifications. This direct growth is challenging due to the large lattice mismatch, the polarity switch and the thermal coefficient difference between Si and III-V materials which induce dislocations, antiphase boundaries and cracks. We have grown a two-step GaSb layer directly on nominal (001)-Si substrate by MOCVD. We cleared the emerging antiphase boundaries for a 250nm thick GaSb layer by optimizing the growth parameters and the nucleation layer thickness. Atomic Force microscopy disclosed a surface RMS roughness as low as 0.5nm for 470nm of GaSb. X-Ray diffraction revealed for a 470 nm thick GaSb layer a full-width-at- half-maximum (FWHM) of the (004) GaSb peaks of 550 arcsec. Crystalline quality investigation have been pursued by transmission electronic microscopy characterizations. The surface defect density has been evaluated to 10^9 cm-2 for a 900 nm GaSb thick layer with top-view images whereas the cross section images disclosed an array of 90° dislocations at the GaSb/Si interface. Photoluminescence is up at room temperature despite the presence of these dislocations so this layer can be the first step to grow optoelectronic devices. GaSb layers grown directly on nominal Si substrate present a good set of electrical and optical properties. Therefore GaSb is a candidate to perform optoelectronic and nanoelectronic devices on 300 mm Si substrate.

M.7.3
12:00
Authors : Marie COSTE1, Timothée MOLIERE1, Geraldine HALLAIS1, Laetitia VINCENT1, Nikolay CHERKASHIN2, Daniel BOUCHIER1, Charles RENARD1
Affiliations : 1Centre de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Sud, Université Paris-Saclay, C2N - Orsay, 91405Orsay cedex, France 2CEMES-CNRS and Université de Toulouse, 29 rue J. Marvig, 31055 Toulouse, France

Resume : Because of GaAs properties such as high electronic mobility and direct band gap, its integration on Si substrate has been studied for fields such as high mobility electronics and integration of novel functionalities in photonics. GaAs integration on Si substrate is a major challenge due to the formation of dislocation (4% lattice mismatch) and other defects like anti-phase domains due to their polar/non polar interface nature. We have previously shown the possibility to integrate GaAs µ-crystal without dislocation and anti-phase domains by epitaxial lateral overgrowth (ELO) from randomly dispersed Si nano-openings. Nevertheless this integration technique leads to the systematic formation of two twins on Si (001). Thanks to the use of a germanium nano-seed which fills completely the nano-opening and begins to wet silica, we have shown the possibility to avoid such twin formation. Besides, because of an easier nucleation with germanium compared with gallium arsenide, the density of filled Si nano-openings is drastically increased. Thus, this procedure allows us to obtain the ELO of GaAs crystals from every Si nano-openings on Si patterned substrate. Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) had been used to observe the crystalline structure; Energy Dispersive X-rays spectrometry (EDX) analysis had been performed in order to localize the Ge nano-seed. These different results will be presented and discussed during the communication.

M.7.4
12:15
Authors : R. Alcotte1,2, T. Cerba1,2, O. Abouzaid1,4, M.L. Touraton1,2,6, M. Martin1, S. David1, F. Bassani1, J. Moeyaert1, B. Salem1, S. Cheng5, M. Liao5, H. Liu5, Y. Bogumilowicz2, D. Dutartre5, X. Bao7, JB Pin7,E. Sanchez7, T. Baron1,
Affiliations : 1 CNRS-LTM, Grenoble, France 2 CEA-LETI, Grenoble, France 3 Applied Materials, Santa Clara, California, United States 4 Faculté des Sciences et Technique de Fès, Maroc 5 University College London, England 6 STMicroelectronics Crolles, Grenoble 7 Applied Materials, santa Clara, USA

Resume : The integration of III-V materials with high carrier mobility and direct band gap on silicon substrates is an important issue for future microelectronic, optoelectronic and photovoltaics devices. Two different approaches are currently developed. The first one is based on III-V layers transfer, previously grown on a III-V substrate,onto a Si substrate. The second one is the direct heteroepitaxy of III-V compounds on Si(100) wafers. However the growth of III-V on silicon generates defects in the layer such as threading dislocations (TD), antiphase boundaries (APBs) and stacking faults. These defects deteriorate the physical properties of materials and decrease the device performances. In the same way, forming low resistive contacts is mandatory to obtain high performance devices. We have developed a specific Si(100) surface preparation to promote the formation of double step surfaces and hence reduce and/or promote the annihilation of antiphase boundaries. Using this process, thin (below 100 nm) GaAs buffer layer without APB are obtained on standard Si(100) 300 mm wafers. Then we have focused our effort to decrease the threading dislocation densities to be compatible with devices requirements. We will show also our latest developments on selective epitaxy and InAs quantum dots formation. Contacts issues will be also treated via doping optimization where high doping level around 5x1019 cm-3 could be obtained for n-type In53Ga47As and 2x1020cm-3 for p-type GaAs. It leads to contact resistivity in the 10-7 Ohm.cm2 range for both types. Finally we will show the realization of an InAs quantum dots laser grown by molecular beam epitaxy on our GaAs buffer layers on Si(100).

M.7.5
12:30 Lunch Break    
 
M-8: Heteroepitaxy and Nanoelectronics II : tba
14:00
Authors : Mallet N.1, Pezard J.1, Lecestre A.1, Scheid E.1, Cristiano F.1, Baron T.2, Fanciulli M.3, Larrieu G.1
Affiliations : 1. LAAS CNRS Université de Toulouse, Toulouse, France; 2. CNRS, LTM, Grenoble, France; 3. University of Milano – Bicocca, Milano, Italy

Resume : Combining high mobility channels with new device architectures such as vertical gate-all-around transistors is a seducing approach to pursue the downscaling beyond the 5 nm-node. GaAs is a promising candidate thanks to its high carrier mobility and its low electronic noise. Nevertheless, some challenges at material / device integration are still remaining: (i) high density of III-V nanowires on Si (ii) high quality high-k dielectric on nanowires (iii) low resistive CMOS compatible contacts. (i) We demonstrated for the first time vertical GaAs nanowire arrays on Si(100) substrate by a top-down approach with very high reproducibility in diameter and morphology. A digital etch protocol has been developed to reduce the diameter of the nanowires, overcoming the lithography’s limit of resolution. (ii) High interface quality was obtained with sulfur passivation and in-situ removing of native oxide prior to ALD of 5 nm thick Al2O3. The interface defects were studied after a post-deposition annealing through capacitive characterizations. The analysis by HR-TEM of the Al2O3 layer implemented on vertical GaAs NWs showed a very uniform Al2O3 layer with a sharp interface (no IL), and, based on chemical analysis, the absence of metal diffusion. (iii) Electrical contacts have been developed based on CMOS compatible alloyed contacts based on comparative studies of various metals and annealing conditions. The best candidate for carrier injection has been implemented on vertical nanowires.

M.8.1
14:15
Authors : Thomas Riedl 1,2, Vinay Kunnathully 1,2, Alexander Karlisch 1,2, Dirk Reuter 1,2, Jörg K.N. Lindner 1,2
Affiliations : 1. Paderborn University, Department of Physics, Warburger Straße 100, 33098 Paderborn, Germany 2. Center for Optoelectronics and Photonics Paderborn (CeOPP), Warburger Straße 100, 33098 Paderborn, Germany

Resume : III-V semiconductor layers are commonly used for optoelectronic applications such as light emitting devices as these materials have direct bandgaps of variable size and high carrier mobilities. However, direct integration on Si substrates is challenging because of the presence of extended defects, which form as a consequence of the lattice misfit as well as thermal expansion coefficient and polarity mismatches. An efficient approach to strongly reduce the density of these defects is the aspect ratio trapping method, which allows to localize the defects close to the heterointerface by means of a nanopatterned mask. Concerning the shape of the mask openings, round holes are particularly promising, because in contrast to the frequently employed trenches the sidewalls of holes can trap defects much more efficiently. In the present contribution we analyze the MBE growth of group III arsenides on SiNx nanohole mask patterned Si(111) substrates. The nanohole masks are fabricated by using nanosphere lithography and reactive ion etching of PECVD deposited SiNx films. Transmission electron microscopy is employed to study the structure of the heterointerfaces, and the propagation and trapping of defects. For examining the crystalline quality of the grown layers we use X-ray diffraction. In particular, the influence of the SiNx hole dimensions on the growth and layer quality is investigated.

M.8.2
14:30
Authors : Po-Chun Hsu1,2, Eddy Simoen1,3, Geert Eneman1, AliReza Alian1, Yves Mols1 Marc Heyns1,2
Affiliations : 1. IMEC, Kapeldreef 75, 3001, Leuven, Belgium 2. KU Leuven, Department of Materials Engineering, Kasteelpark Arenberg 44, 3001 Leuven, Belgium 3. Ghent University, Department of Solid State Sciences, Krijgslaan 281 S1, 9000 Gent, Belgium

Resume : The defects introduced during heteroepitaxy are one of the major problems in InGaAs-based HEMT, TFET and optical devices on III/V substrate. Therefore, understanding the impact of crystalline defects on their electrical performance catches more and more attention. However, the deconvolution and the electrical properties characterization of the different type of defects is still a challenge. In this work, we developed a specific P+ N junction structure with top-top self-alignment contact for investigating growth-induced defects during the heteroepitaxy of InGaAs by MOVPE. The comparison in defect densities (Ddefect<1E5 cm-2 versus Ddefect~1E9 cm-2) due to the use of different substrates (lattice-mismatch f = 3.5%, 0.02% and 0%), and in doping elements(Si,Se) has been studied by DLTS, T-dependent IV&CV, XRD and AFM. We report two majority hole traps (ΔET = 0.24, 0.54eV) and one electron trap (ΔET = 0.45eV) in the sample with the larger lattice-mismatch. In addition, we found the leakage current in reverse-bias region increasing nonlinearly with the defect density. Besides, we demonstrate how to discriminate a P N diode with a Schottky contact which is often present in III/V materials due to fermi-level pinning. Finally, by extracting the relevant parameters of the defects, we built a TCAD model to estimate the defects’ impact with good experimental agreement, which can be used further in advanced nano-scale devices.

M.8.3
14:45
Authors : Anurag Vohra1,2, Geoffrey Pourtois2,5, Jonatan Slotte3, David Kohen4, Roger Loo2 and Wilfried Vandervorst1, 2
Affiliations : 1K.U. Leuven, Dept. of Physics, Celestijnenlaan 200D, 3001 Heverlee, Belgium 2imec vzw, Kapeldreef 75, 3001 Heverlee, Belgium 3Department of Applied Physics, Aalto University, P.O. Box 14100, FI-00076 Aalto, Finland 4ASM, Kapeldreef 75, 3001 Leuven, Belgium 5Department of Chemistry, Plasmant Research Group, University of Antwerp, B-2610 Wilrijk-Antwerp, Belgium

Resume : We report theoretical and experimental studies concerning the interaction of point defects (vacancies) with dopants (Sn & P) in epitaxial GeSn:P films. The formation of P-V clusters is the main source behind the deactivation of donors at high P concentrations (>8x1019 at./cm3) in as-grown Ge layers. Co-doping with Sn boosts the active P concentration in Ge1. However, the interplay between Sn and vacancies and their role in the activation process of P remains unclear. In order to gain insight in their relation, we examined the vacancy trapping proficiency of Sn and P in germanium films using first-principles simulations and corroborate our findings with positron annihilation studies on GeSn:P films. The later were epitaxially grown by chemical vapor deposition with different concentration of Sn. Interaction energies for two substitutional Sn (P) atoms in Ge for coordinations varying up to 8th nearest neighbor were investigated. In presence of a vacancy, the enthalpy of formation of Snn-V & Pn-V clusters predict that the formation of dopant-vacancy clusters is more stable than a pure substitutional incorporation of P atoms, leading to a deactivation of the dopant. Nonetheless, μHall measurements indicated a rise in active P concentration with increasing Sn%. Doppler Broadening Spectroscopy (DOBS) measurements validate the presence of strong trap in GeSn:P layers. 1. Vanhellemont, J. & Simoen, E. Mater. Sci. Semicond. Process. 15, 642–655 (2012).

M.8.4
15:00
Authors : R. Maurand, X. Jehl, D. Kotekar-Patil, A. Corna, H. Bohuslavskyi, R. Lavieville, L. Hutin, S. Barraud, M. Vinet, M. Sanquer, S. De Franceschi.
Affiliations : Univ. Grenoble Alpes, INAC-PHELIQS, F-38000 Grenoble , France CEA, INAC-PHELIQS, F-38000 Grenoble, France CEA, LETI MINATEC campus, F-38000 Grenoble, France

Resume : We report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. R. Maurand et al. Nature Comm. 2016 DOI: 10.1038/ncomms13575

M.8.5
15:30 Coffee Break    
 
M-9: Materials for Opto- and Nanoelectronics II : tba
16:00
Authors : Jean-Pierre RASKIN
Affiliations : Université catholique de Louvain (UCL) Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM)

Resume : Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency commercial applications pushing the limits of CMOS technology. Thanks to the introduction of the trap-rich high-resistivity SOI substrate on the market, the ICs requirements in term of linearity for RF switches, for instance, are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this lecture, their analog/RF behavior is described and compared. Both show pretty similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances. The use of specific RF test structures at the early stage of a technological node development is of first importance to analyze the transistor parasitic resistances and capacitances, the transistor cutoff frequencies, the self-heating, and the substrate coupling and non-linear behavior. The relative impact of the transistor and the passive elements and interconnections on the small- and large-signal RF performance of SOI RF switches and power amplifier will be presented.

M.9.1
16:30
Authors : J.Schlipf 1, J.L.Frieiro 2, I.A.Fischer 1, E.Martín 3, C.Serra 4, A.Benedetti 4, J.Schulze 1, S.Chiussi 2
Affiliations : 1 Institut für Halbleitertechnik (IHT), Universität Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany; 2 Dpto. Física Aplicada, Univ. de Vigo, Rua Maxwell s/n, Campus Universitario Lagoas Marcosende, 36310 Vigo, Spain; 3 Dpto. Mecánica, Máquinas, Motores Térmicos y Fluidos, Univ. de Vigo, Campus Universitario, 36310 Vigo, Spain; 4 CACTI, Univ. de Vigo, Campus Universitario, 36310 Vigo, Spain

Resume : We examine the influence of SiO2 hard masks on the formation of SiGe, GeSn and GePb alloys by Pulsed Laser Induced Epitaxy, a method allowing fast processing and in-situ monitoring. Main objectives are to study the spatial distribution of elements, crystallinity and strain as well as the possible under etching of Ge after mask removal. Limitations and quality characteristics for alloy formation due to the use of conventional SiO2 hardmask patterns are evaluated using Pulsed Laser Induced Epitaxy (PLIE). The samples were Si(100) wafers with a 200 nm thick epitaxial Ge layer, grown through Molecular Beam epitaxy (MBE), that were patterned with a SiO2 hardmask of different window sizes. Samples with and without these patterns were PLIE treated with and without depositing thin Sn or Pb layers on top , through thermal evaporation. PLIE itself was performed using ArF excimer laser pulses of 193 nm wavelength to induce melting and resolidification processes, taking the crystal structure of the Si(100) substrate below as seed. Monitoring of the melt/resolidification process was done “in situ” by Time Resolved Reflectivity (TRR). Dependence of material properties on number of laser pulses and pulse energy density are evaluated, mainly via Atomic Force Microscopy and Raman Spectroscopy. Experimental results were compared with theoretical simulations of involved spatial and temporal temperature gradients, calculated using Finite Element Methods (FEM). Evaluation of the extensive material characterization and of the simulation results is done, examining the fabrication quality, thus the feasibility of future integrated laser devices.

M.9.2
16:45
Authors : Koji Yamada, Masami Matsuda,
Affiliations : Future Product, 13-8 2-chome, Kita-Hara, Asaka, Saitama, Japan

Resume : We had been investigated nano-scale SiO2 composit powders to reform it into poly crystals without voids, which successfully sealed the mirrors in LED and prevented from corrosions or degradations. This investigation was applied for an element of the dielectrically induced barrier discharge (DBD) in air by dint of the very small amount of defects or voids in the form of membrane with thicknesses of 100-300 micro-m. The generations of active gas of N2+ were easily obtained with a long life DBD element which consumes the electric power as small as 1W of order. The active gasses of N2+ are able to use it for sterilization. In addition to these investigations, we used these membranes for the thermal radiations from the metal surfaces. We found that the optimal cooling conditions of the membranes exist in the thickness range in between 5 and 20micro-m. In these investigations, the composite materials of SiO2 together with many other material of C, TiO2 etc. were tested. Here, the modified black-body radiations were sensitively detected by using thermisters as a function of elapsed times with sub-second responses. We plausibly observed the detaching/attaching phenomena of massive molecule clusters from the metal surface as sudden changes in sample temperature decreases/increases just like in noises in the detectors.

M.9.3
17:00
Authors : Marco Salvalaglio (1)(2), Rainer Backofen (1), Meher Naffouti (3)(4), Thomas Bottein (3), Mario Lodari (5), Thomas David (3), Abdelmalek Benkouider (3), Ibtissem Fraj (4), Luc Favre (3), Antoine Ronda (3), Isabelle Berbezier (3), David Grosso (3), Marco Abbarchi (3), Monica Bollani (5), Axel Voigt (1)
Affiliations : (1) Institute of Scientific Computing, Technische Universität Dresden, 01062 Dresden, Germany; (2) IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany; (3) Aix Marseille Université CNRS Université de Toulon IM2NP UMR 7334, 13397 Marseille, France; (4) Laboratoire de Micro-optoélectronique et Nanostructures Faculté des Sciences de Monastir Université de Monastir 5019 Monastir, Tunisia; (5) IFN-CNR, L-NESS laboratory,via Anzani 42, 22100 Como, Italy

Resume : Thin solid films are rarely stable when annealed even below their melting temperature. Under the action of surface diffusion, atoms move away from the film edges leading to the retraction and breaking of the film, eventually forming isolated islands. This process occurs during thermal treatment of ultra-thin silicon films on insulators (UT-SOI), limiting their applications in several microsystems. Moreover, the self-assembled structures forming at the end of the process show too large randomness in positioning and size dispersion to be exploited for targeted applications, such as optical meta-surfaces [1]. Here, thanks to a synergistic theoretical and experimental investigation, we illustrate a method to control the dewetting of UT-SOI, delivering nanostructures with determined positions, sizes and shapes [2]. Predictive, 3D phase-field (PF) simulations, accounting for the dominant role of surface diffusion-limited kinetics [3], are adopted to enlighten the mechanism underlying the process and assess the outcomes of experiments. Indeed, we demonstrate that a fine control over the final structures is achieved when combining Si patches with ad hoc initial patterning of the thin film. Moreover, PF simulations are proven to offer a tool for further engineering this hybrid top-down/bottom-up self-assembly method. [1] C. V. Thomson, Ann. Rev. Mater Sci. 42, 399 (2012). [2] M. Naffouti et al., Small 44, 6115 (2016). [3] M. Salvalaglio et al., Cryst. Growth Des. 15, 2787 (2015).

M.9.4
17:15
Authors : Y. Mols, J. Bogdanowicz, P. Favia, P. Lagrain, W. Guo, H. Bender, B. Kunert
Affiliations : imec, Kapeldreef 75, B-3001 Leuven, Belgium

Resume : We report on the uniform selective area growth of InAs and GaSb by metal-organic vapour phase epitaxy on a standard 300 mm shallow trench isolation (STI) template, i.e. a SiO2 pattern of narrow trenches on Si with a {111}-faceted V-groove at the bottom. Direct InAs nucleation on the Si V-grooves is developed. A 60° interfacial misfit dislocation array is formed at the InAs/Si interface and minimizes threading dislocation generation. GaSb grown on a GaAs buffer suffers from twin formation. The twin density is found to decrease with increasing growth temperature. Uniform high-quality GaSb fins with a maximized GaSb volume inside the trench are realized through growth on a low-temperature III-As seed instead of the full GaAs buffer. Both GaAs and InAs seeds are compared. High resolution x-ray diffraction reciprocal space maps show that the InAs and GaSb material is nearly completely relaxed. The resistivity values of as-grown intrinsic and Si-doped InAs and GaSb fins are estimated by micro-four-point probe measurements, requiring no additional device processing. The resistivity of GaSb follows a different trend depending on the seed used. The obtained results are encouraging developments towards the integration of vertical nanowire III-V (T)FETs and other applications on Si.

M.9.5
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09:00 Plenary Session - Main Hall    
12:30 Lunch break    
 
M-10: 2D Materials and Devices : Aurelie Spiesser
14:00
Authors : M. Houssa1, K. Iordanidou1, A. Lu2, A. Dabral1,3, G. Pourtois3, V.V. Afanas'ev1, and A. Stesmans1
Affiliations : 1 Department of Physics and Astronomy, University of Leuven, B-3001 Leuven, Belgium 2 MathAM-OIL, AIST, Sendai 980-8577, Japan 3 imec, 75 Kapeldreef, B-3001 Leuven, Belgium

Resume : Transition metal dichalcogenides (TMD) such as MoS2, MoSe2, WS2, WSe2,... are currently attracting considerable interest due to their promising applications in future nanoelectronic devices, like field-effect transistors, photodetectors, solar cells,...[1-3]. In this presentation, an overview about the structural, electronic and transport properties of 2D (monolayer) TMD will be given, comparing various experimental results with predictions from first-principles simulations, based on density functional theory. We will first discuss the ballistic transport properties of TMD monolayers and heterostructures, for their potential use in field effect devices, like double-gate MOSFETs and tunnel FETs [4-6]. Obviously, the electronic and transport properties of TMD are affected by the presence of intrinsic and extrinsic defects. The impact of various intrinsic defects (vacancies and antisites) on the electronic properties of 2D TMD will be next discussed. The computed g-tensors of these defects will be compared to experimental values, reported recently from ESR experiments on MoS2 [7,8], in an attempt to identify these defects. The interaction of these defects with hydrogen will also be addressed. Finally, the oxidation of defect free and defected 2D TMD will be discussed, and differences in the oxidation mechanism of MoS2 and HfS2, as predicted from molecular dynamics simulations [9,10], will be highlighted. [1] S.Z. Butler et al., ACS Nano 7, 2898 (2013). [2] G. Fiori et al., Nature Nanotech. 9, 768 (2014). [3] F. Schwierz et al., Nanoscale 7, 8261 (2015). [4] A.K.A. Lu et al., Appl. Phys. Lett. 108, 043504 (2016). [5] A.K.A. Lu et al., J. Appl. Phys. 121, 044505 (2017). [6] A.K.A. Lu et al., ACS Appl. Mater. Interfaces 9, 7725 (2017). [7] A. Stesmans et al., Nanoscale Res. Lett. 12, 283 (2017). [8] M. Houssa et al., Appl. Surf. Sci. 416, 853 (2017). [9] K. Iordanidou et al., ECS J. Solid State Sci. Tech. 5, Q3054 (2016). [10] K. Iordanidou et al., Phys. Stat. Sol. RRL 10, 787 (2016).

M.10.1
14:30
Authors : Salim El Kazzi, Wouter Mortelmans, Iuliana Radu, Marc Heyns and Clement Merckling
Affiliations : IMEC, Kapeldreef 75,3001, Heverlee, Belgium

Resume : Transition-metal dichalcogenides (TMDs) are opening an era of research innovation in different fields ranging from stretchable (opto)electronics, (bio)sensors, water treatment and clean energy. In order for them to gain industry, bottom up techniques based on both chemical or physical deposition are being used to grow these materials on large area commercial templates. Due to the unique Van der Walls interactions that MX2 offer, these techniques have succeeded to demonstrate the synthesis of 2D materials on both amorphous or crystalline templates. However, most of the bottom-up 2D MX2 layers till now present inferior crystalline quality compared to exfoliated flakes. This is due to the formation of small grain sizes with different in-plane orientation due to the absence of an epitaxial relationship with the substrate as well as a poor MX2 grain crystalline quality caused by non-optimized growth conditions. In this work, we present a study to insure an epitaxial relationship between MX2 and the surface underneath. We particularly explore the crystalline templates (like Sapphire and AlN) surface engineering impact on the epi-layer of WSe2 grown by GS-MBE. The influence of the in-plane hexagonal symmetry, step edges and surface passivation on the nucleation process of 2D materials are discussed. After that, the work is extended on the investigation of the 2D growth parameters (growth rate, temperature and pressure) in the target to achieve high quality crystalline 2D layers

M.10.2
14:45
Authors : Joachim Knoch
Affiliations : RWTH Aachen University, Institute of Semiconductor Electronics

Resume : Two-dimensional materials such as graphene and transition metal dichalcogenides have recently attracted a great deal of interest since they potentially enable the realization of ultimately scaled field-effect transistors based on planar fabrication technology. Furthermore, the ultrathin channel layer thickness is also beneficial for advanced device concepts such as band-to-band tunneling field-effect transistors (TFETs) that potentially facilitate integrated circuits that consume less power compared to ICs based on conventional CMOS technology. However, appropriate doping of 2D materials, particularly when targeting TFETs, is not necessarily obvious. On the other hand, using gate electrodes instead of static doping allows the realization of potential landscapes within the 2D material that can be exploited to study, e.g., the metal-2D material contact properties as well as to realize a dynamic adjustment of the functionality of the devices. Based on a silicon platform featuring multiple, nanoscale gates, recent results on 2D material transistors will be presented.

M.10.3
15:15
Authors : Clement Porret 1, Claudio Luraschi 1-2, Thomas Nuytten 1, Xiangyu Wu 1, Inge Asselberghs 1, Ken Verguts 1-3, Stefan De Gendt 1-3, Steven Brems 1, Cedric Huyghebaert 1, Roger Loo 1
Affiliations : 1 imec vzw, Kapeldreef 75, 3001 Leuven, Belgium; 2 Politecnico di Milano, Polo di Como, Via Anzani 42, 22100 Como, Italy; 3 Departement Chemie, Katholieke Universiteit Leuven, Celestijnenlaan 200F, B-3001 Leuven, Belgium

Resume : The uniform and controlled growth of high-quality graphene on Si wafers is a challenge for the fabrication of devices in large volumes. In this contribution, we show that Reduced-Pressure Chemical Vapor Deposition is a promising technique for the elaboration of graphene on large Ge/Si wafers. Methods for efficient graphene transfer are also investigated and used to assess the quality of the grown layers. We first establish suitable conditions for the deposition of graphene on bulk Ge wafers and relaxed Ge/Si virtual substrates. Graphene growth is performed using CH4 and H2 gases in a 200 mm production reactor (ASM Epsilon®2000). The growth behaviors of graphene on Ge/Si(001) and on Ge(110) and Ge/Si(110) are very different. Graphene domains elongate along the [-110] direction on Ge(110), following the anisotropic pattern formed on the surfaces at high temperature, while they expand in several directions and induce the formation of facets on Ge/Si(001). Following the growth, graphene layers are transferred to standard 90 nm SiO2/Si samples in order to evaluate their structural and electrical properties using Raman spectroscopy and back-gated structures. This allows benchmarking the quality of transferred graphene/Ge against graphene elaborated on different templates. Using our optimized growth and transfer processes, mobility values as high as 1500-2000 cm2.V-1.s-1 are demonstrated, meaning that graphene/Ge has a quality comparable to that of commercially available graphene.

M.10.4
15:30 Coffee Break    
 
Joint session L&M: Integration and processing challenges: Germanium : Ray Duffy
16:00
Authors : Slawomir Prucnal
Affiliations : Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum Dresden-Rossendorf, Germany

Resume : One of the main obstacles towards wide application of Ge in nanoelectronics is the lack of an efficient doping method for the fabrication of heavily doped Ge layers with well controlled junction depth. In fact, n-type doping of Ge is a key bottleneck in the realization of advanced negative-channel metal-oxide-semiconductor (NMOS) devices. Here an overview of different doping techniques will be presented. Special attention will be focused on the use of ion implantation followed by flash-lamp (FLA) annealing for the fabrication of heavily doped Ge. In contrast to conventional annealing procedures, rear-side FLA leads to full recrystallization of Ge and dopant activation independently of pre-treatment. The maximum carrier concentration is well above 10^20 cm-3 for n-type and above 10^21 for p-type doping. The recrystallization mechanism and the dopant distribution during rear-side FLA are discussed in detail. In this work, we report on the strong mid-IR plasmon absorption from heavily P-doped Ge thin films and superconductivity in Ga and Al doped Ge obtained by non-equilibrium thermal processing. The mid-IR plasmon spectral response at room temperature from those samples was characterized by means of Fourier transform infrared spectroscopy. It is proven that the position of the plasmonic resonance frequency signal can be tuned as a function of the P concentration.

M.LM.1
16:30
Authors : R. Milazzo(1), G. Impellizzeri(2), A. La Magna(3), D. Scarpa(4), S. Boninelli(2), A. Sanson(1), D. De Salvador(1), M. Linser(1), C. Carraro(1), A. Andrighetto(4), A. Portavoce(5), D. Mangelinck(5), J. Slotte(6), V. Privitera(2), G. Fortunato(8), A. Carnera(1), E. Napolitani(1)
Affiliations : (1) CNR-IMM Matis and Dipartimento di Fisica e Astronomia, Università di Padova, via Marzolo 8, 35131 Padova, Italy; (2) CNR-IMM Via S Sofia 64, I-95123 Catania, Italy; (3) CNR-IMM , Z.I. VIII Strada 5, 95121 Catania, Italy; (4) INFN Laboratori Nazionali di Legnaro, Italy; (5) IM2NP, CNRS-Universités d?Aix-Marseille et de Toulon, Marseille, France; (6) Department of Applied Physics, Aalto University, P.O. Box 15100, FI-00076 AALTO, Finland; (7) Dipartimento di Fisica e Astronomia, Università di Catania, Via S Sofia 64, I-95123 Catania, Italy; (8) CNR-IMM, Via del Fosso del Cavaliere 100, 00133 Roma, Italy;

Resume : Due to its high carrier mobility, germanium lately attracted a renewed interest in various fields of material science such as nano-electronics, photonics, detectors, etc. However, Ge-based devices often requires very high doping levels ( > 1e20 cm-3), which are above the solubility limit for most of the dopants. Besides, effective downscaling beyond 10 nm needs ultra-shallow junctions, which are challenging especially for donors, due to their high diffusivities. For this purpose, Laser Thermal Annealing (LTA) in the melting regime is the most promising doping technique as it induces ultra-fast liquid phase epitaxial regrowth, while confining the diffusion within the molten layer. Indeed, LTA holds the records of activation for P, As and Sb, being ~ 1e21 cm-3 in the latter case. Latest studies on p- (by means of B or Al) and n-type (using As) doping of Ge by LTA following ion-implantation will be presented thanks to advanced characterizations, in terms of chemical (1D and 3D), electrical and strain pro?ling with nanometer resolution. In particular, fundamental mechanisms such as non-equilibrium diffusion, dopant incorporation, clustering and point defects generation will be discussed with special care on strategies for improving the electrical activation, together with issues about contaminations and thermal stability. These experimental results are relevant for modeling the LTA process in Ge in view of its implementation toward future technologies.

M.LM.2
16:45
Authors : S. Boninelli1, R. Milazzo2, R. Carles3, F. Houdellier3, R. Duffy4, K. Huet5, E. Napolitani1,2, A. La Magna6, and F. Cristiano7
Affiliations : 1 IMM CNR, via S. Sofia 64, Catania, Italy 2 Dipartimento Fisica e astronomia, Università di Padova, Via F. Marzolo 8, 35131 Padova, Italy 3 CEMES-CNRS, 29, Rue Jeanne Marvig, 31055 Toulouse, France 4 Tyndall National Institute, University College Cork, Lee Maltings, Cork, Ireland 5 Laser Systems and Solutions of Europe (LASSE), Dainippon Screen Group, 14-38 Rue Alexandre, 92230 Gennevilliers, France 6 IMM CNR, Zona industriale, Strada VIII 5, 95100, Catania, Italy, 7 LAAS-CNRS, 7 av. du Col. Roche, F-31400 Toulouse, France

Resume : Laser Thermal Annealing (LTA) at various energy densities was used to recrystallize and activate Ge doped with P by ion implantation. Conventional techniques, such as Secondary Ion Mass Spectrometry, Raman analyses and Transmission Electron Microscopy, were employed to study the dopant diffusion and the structural modification induced during the recrystallization. After LTA at low energy densities, the P distribution was mainly localized in the polycrystalline Ge left as a residual damage induced by the ion implantation. Conversely, a fully activated P diffusion in a perfectly recrystallized material was observed after annealing at higher energy densities. The introduction of a dopant atom in substitutional position often results in generation of strain depending on its configuration within the matrix lattice. Thus, the combination of High Resolution X-Ray Diffraction and Convergent Beam Electron Diffraction techniques allowed to measure an extremely low compressive strain and quantify the strain per each substitutional P atom. In conclusion, these studies render the LTA of widespread interest not only for applications in Ge based technology but also for conducting fundamental studies.

M.LM.3
17:00
Authors : V. Boldrini1)2), D. De Salvador1)2), S. Carturan1)2), G. Maggioni1)2), E. Napolitani1)2), D.R. Napoli2)
Affiliations : 1) Dipartimento di Fisica e Astronomia, Università degli Studi di Padova, via Marzolo 8, I-35131 Padova, Italy; 2) INFN-LNL Viale dell’Università 2, I-35020 Legnaro, Padova, Italy

Resume : The fabrication of homogeneously doped germanium layers characterized by high electrical activation is currently a hot topic in many fields, such as microelectronics, photovoltaics, optics and radiation detectors. P spin-on-doping (SOD) technique has been implemented on Ge wafers, by developing an accurate protocol for the spin coating and the curing process of the SOD coating. Many parameters turned out to affect the degree of reticulation reached by the coating, the morphology of Ge surface and the amount of dopant available for diffusion. In detail, the parameters to be controlled are: SOD film thickness, the humidity level in curing atmosphere, curing temperature and time. P diffusion has been carried out through peculiar spike annealing treatments inside a standard tube furnace. The diffusion profiles and dopant electrical properties have been measured through SIMS and Van der Pauw – Hall electrical measurements respectively. Thanks to the optimization of all the involved parameters, continuous and homogeneously doped Ge layers were obtained, without any surface damage. Phosphorus diffusion profiles are box-like, with tunable concentration and thickness and they are totally electrically active up to a maximum carrier concentration of 5x1019 cm-3.

M.LM.4
17:15
Authors : F. Sgarbossa 1) 2), D. De Salvador 1) 2), G. Maggioni 1) 2), S. Carturan 1) 2), V. Boldrini 1) 2), E. Napolitani 1) 2), D. R. Napoli 2), W. Raniero 2)
Affiliations : 1) University of Padova, Department of Physics and Astronomy, Via Marzolo n. 8, Padova Italy 2) Istituto Nazionale Fisica Nucleare, Laboratori Nazionali di Legnaro, Viale dell’Università 2, Legnaro Italy

Resume : Small bandgap and high mobility of charge carriers have been recently making germanium (Ge) more and more interesting in several application fields, for mid-infrared and gamma radiation detectors, photovoltaics and nano-electronics. For this last application, nano scale doping is a challenging task and monolayer doping from a chemical source is one of the most promising routes to face it. Applying this technique to Ge is therefore technologically relevant. In this work, we report about a physical method for the formation of a Sb monolayer (ML) on Ge surface by means of thermal evaporation from a Sb layer sputtered on Si, used as a remote source. Thanks to RBS analysis, we show that above 600°C, the Ge surface is stably covered with a Sb ML and up to 780°C, demonstrating a strong Sb affinity with Ge surface. At lower temperatures a thicker Sb/Ge alloy layer forms. ML formation is peculiar of Ge surface being not present on Si. SEM and AFM characterizations reveal that Ge surface has a good morphology with no surface defects, of crucial importance for nano-electronics doping process. The most relevant point is that, by means of SIMS chemical profiling we have demonstrated that Sb ML acts as an effective diffusion source, in agreement with with equilibrium diffusivity data reported in literature. According to the above results, Sb ML formation is an intriguing phenomenon highly promising for future nanoscale Ge doping processes.

M.LM.5
18:00 Best Student Presentation Award & Reception 18:00-21:00 (Main Hall)    
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Joint session L&M: Metrology at the nm scale : Pierre Eyben
09:00
Authors : Ronald Gull(1), Victor Moroz(2), Ricardo Borges(2), Terry Ma(2)
Affiliations : (1) Synopsys Switzerland LLC; (2) Synopsys Inc.

Resume : Simulation and modeling are indispensable for the semiconductor technology development in leading CMOS technologies. The scope of these simulation techniques, summarized as technology aided computer design (TCAD) has dramatically increased in the last decade, as new materials were constantly introduced, combined with an ever stronger coupling of technology with design decisions. Starting from current CMOS technology, we review in a study the aspects of scaling options down to the 5/3/2nm technology nodes. The complex optimization needs to include the physics on quantized electron states, all the way to design decisions on how many tracks high the standard cell needs to be designed. The strong interaction of the device with the middle end of line contacting scheme, up to the lower level interconnect for a library cell, calls for a holistic analysis of the library cell, as simplified CV/I metrics can no longer be applied. Looking forward TCAD needs to connect electronic properties of materials with atomistic and microscopic simulations, link in a hierarchical approach to continuum descriptions, and finally combine the results in system level performance metrics. We project that added to the multi-scale complexity, the scope of simulation is further growing from classical process and device modeling, to chemical surface reaction and mechanical simulation, or full process integration modeling, all based on fundamental material analysis.

M.LM.6
09:30
Authors : G. Brémond
Affiliations : Université de Lyon, Institut des Nanotechnologies de Lyon, CNRS UMR5270, INSA de Lyon, Bat. Blaise Pascal, 7 avenue Capelle, F-69621 Villeurbanne Cedex, France.

Resume : The continuing shrinkage of semiconductor devices toward nanoscale and their increased functionality using new materials and architectures tackling miniaturization, power consumption and processing speed challenges has prompted a strong need for high-resolution characterization tools capable of mapping properties of interest with nanoscale resolution. Methods to quantitatively determine the doping profile in semiconductor nanowires (NW) are strongly requested for understanding the doping incorporation in such one-dimensional structures and so as for developing NW technology. Impurity (as dopant but not only) characterization could be made by direct method based on chemical analysis using TOFSIMS , ATP , holography TEM or by indirect method using the properties induced by the impurity as electrical conductivity which play on capacitance , resistance , surface potential, etc… New approach including optical spectroscopy are also emerged and developed. SPM techniques mainly based on electrical measurements as scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM), are promising tools for two-dimensional high resolution carrier/dopant profiling on advanced metrology for future technology nodes of the microelectronics world. Some illustration will be given of 2D/3D doping profiling method especially on semiconductor nanowires technology. This approach will be completed by the possibility of using SPMs to characterize the interfaces between different materials (doping, trapping) ) and to acquire chemical information using the advantage of optical spectroscopy revealing photoinduced mechanisms as photocurrent, photocapacitance or photoinduced force.

M.LM.7
10:00
Authors : Rosine COQ GERMANICUS 1, Peter DE WOLF 2, Mickaël FEBVRE 2, Philippe DESCAMPS 1
Affiliations : 1: Normandy University ENSICAEN, Unicaen, CRISMAT UMR 65086, 14050 Caen cedex 04, France 2: Bruker Nano Surfaces, 7 rue de la Croix Martre, 91120 Palaiseau, France

Resume : In high integrated Front End of the Line (FEoL) process, the detection, control and quantification of the effective 2D/3D active dopant distributions are a key to optimize the design. Scanning Probe Microscopy (SPM) offers conventional electrical modes such as Conductive, Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy to analyze a biasing probe-sample system where a conductive tip is in contact with the analyzed sample. Despite the capability, repeatability and high spatial resolution of these modes, there are limited to map type and local carrier concentration of semiconductors. Recently Scanning Microwave Impedance Microscopy (sMIM) is developed to extend the range and opens a wider analysis field. sMIM consists of a combination of an Atomic Force Microscope (AFM) with an optimized microwave network analyzer. A probe with shielded co-axial cantilever equipped to a conductive tip is used as local RF sensor, this is the strength of the sMIM. The microwave signal emanates from the tip and interacts with the surface and sub-surface of the analyzed sample. By analyzing the reflected signal, local permittivity and conductivity maps of the probed area are extracted. Electrical properties of semiconductors but also oxides, dielectrics, metals and composites are determined. We demonstrate the capability of the sMIM mode where all FeOL and BeOL (Back End of the Line) layers inside integrated PIN diode structures are revealed.

M.LM.8
10:15
Authors : Komal Pandey, Kristof Paredis, Wilfried Vandervorst
Affiliations : Imec, Kapeldreef 75, 3001, Leuven, Belgium, Instittuut voor Kern- en Stralingsfysica, KULeuven, 3001 Leuven, Belgium ; Imec, Kapeldreef 75, 3001, Leuven, Belgium ; Imec, Kapeldreef 75, 3001, Leuven, Belgium, Instittuut voor Kern- en Stralingsfysica, KULeuven, 3001 Leuven, Belgium

Resume : The power of Scanning Spreading Resistance Microscopy (SSRM) lies in its ability to quantitatively probe carrier concentrations at high resolution. However, it is being challenged by the scaled dimensions of sub 10 nm node devices due to lack of proper understanding of Spreading Resistance (SR) in confined volumes. The limited amount of material, the presence of interfaces, the confined current paths and the difficult back contacts may all impact the total resistance, and hence rendering the carrier quantification faulty. A good fundamental understanding is crucial for future carrier quantification with SSRM. TCAD provides an efficient way for studying the SR in sub-10nm regime for different geometrical set-ups. Here, we report a TCAD study on behavior of SR when confinement is introduced in a cylindrical slab with probe contact at the center of top surface. We report on two types of back contact configurations; one at the bottom surface of cylinder (first) and second at the curved surface (second), analogous to real configurations such as FINFET like structures. It was observed that onset of confinement effect on SR varies significantly across both configurations. In first case it took half as much thickness as it took in second case for 10% deviation in SR from its bulk value. Furthermore, we compare our simulations with experimental data and will discuss in detail the impact of confinement on the SSRM measurement and carrier quantification.

M.LM.9
10:30 Coffee Break    
 
Joint session L&M : tba
11:00
Authors : L. Rigutti, L. Mancini, E. Di Russo, F. Moyon, S. Moldovan, C. Hatzoglou, W. Lefebvre, D. Blavette, F. Vurpillot
Affiliations : Normandie Univ, UNIROUEN, INSA Rouen, CNRS, Groupe de Physique des Matériaux, 76000 Rouen

Resume : Atom probe tomography (APT) has recently emerged as a nano-analysis technique allowing for the reconstruction of the three-dimensional distribution of chemical species with sub-nanometer resolution within volumes of several tens of nm3. The recorded compositional maps allow assessing features such as alloy distributions or heterostructure compositions, shapes and interfaces. From this rich set of information it becomes possible to interpret the electronic and the optical properties of semiconductor heterostructures [1-4]. Nevertheless, it should be kept in mind that the technique also has several limitations due to the physical processes of field evaporation on which it is based, e.g., to cite two of the most important effects: (i) the degradation of the spatial resolution induced by the presence of materials with different evaporation behaviors within the same specimen (e.g., Si and SiO2) and (ii) the degradation of both spatial resolution and compositional accuracy related to the relatively low and sometimes species-specific detection efficiency [4,5]. These effects occur in the measurements under typical conditions of analysis and affect the information provided by APT. This will be shown in the case of selected systems, i.e., AlGaN epitaxial layers, GaN/AlN quantum dots and Si-based MOS transistors. These results will be critically discussed in order to underline what is the impact of the above-mentioned non-ideal features affecting typical APT measurements, and what strategies – especially based on complementary scanning transmission electron microscopy (STEM) analyses - can be adopted in order to reduce it [6,7]. [1] L. Rigutti et al., Nano Lett. 14, 107–114 (2014) [2] L. Mancini et al. Appl. Phys. Lett. 105, 243106 (2014) [3] L. Mancini et al. Appl. Phys. Lett. 108, 042102 (2016) [4] L. Rigutti et al. J. Appl. Phys. 119, 105704 (2016) [5] L. Mancini et al. J. Phys. Chem. C 118 24136 (2014) [6] L. Rigutti et al. Semicond. Sci. Technol. 31(9), 095009 (2016) [7] E. Di Russo et al. under review.

M.LM.10
11:30
Authors : S. Folkersma (a,b,1), J. Bogdanowicz (a), A. Schulze (a), D. H. Petersen (c), O. Hansen (c), H. H. Henrichsen (d), P. F. Nielsen (d) and W. Vandervorst (a,b)
Affiliations : a) IMEC, Kapeldreef 75, B-3000 Leuven, Belgium b) Instituut voor Kern- en Stralingsfysika, KU Leuven, Celestijnenlaan 200D, B-3001 Leuven, Belgium c) Department of Micro- and Nanotechnology, Technical University of Denmark, DTU Nanotech Building 345 East, DK-2800 Kgs. Lyngby, Denmark d) CAPRES A/S, Scion-DTU, Building 373, DK-2800 Kgs. Lyngby, Denmark 1) email address: steven.folkersma@imec.be

Resume : As doped regions in a finFET transistor are confined in small volumes with large surface/volume ratios, dopant incorporation and activation has become size dependent. Therefore, the electrical properties of such nanometer-wide conducting features need to be probed on devices with relevant dimensions and not on blanket films or large pads. As such, regular four-point probe measurements (with probe spacing > 40-500 µm) have become obsolete and one frequently relies on electrical characterization using multiple fins connected by metal contacts on Kelvin resistor or transmission line structures, where information on individual fins is lost. In this paper we demonstrate that, through rigorous data interpretation and refined measurement procedures, a solution based on the micro four-point probe (µ4pp) technique as implemented in the fully automated microHALL®-A300 tool of CAPRES, can be provided to measure the electrical resistance of single nanometer-wide (20-50 nm) fins without the need for metal contacts. The measured fin resistances correlate with the fin widths as measured by transmission electron microscopy and the resistances are shown to be sensitive to sub-nm width variations, allowing for detailed line width variation measurements. This solution opens the possibility to study the impact of sidewall roughness and dimension-dependent epitaxial growth or dopant diffusion/activation, which has so far been hampered by the absence a metrology solution.

M.LM.11
11:45
Authors : G. Laricchiuta, W. Vandervorst, I. Vickridge, M. Mayer, P. Favia, A. Schulze, J. Meersschaut.
Affiliations : K.U.Leuven, IKS, Celestijnenlaan 200D, B-3001 Leuven, Belgium, imec, Kapeldreef 75, B-3001 Leuven, Belgium; K.U.Leuven, IKS, Celestijnenlaan 200D, B-3001 Leuven, Belgium, imec, Kapeldreef 75, B-3001 Leuven, Belgium; Sorbonne Universités, UPMC Univ Paris 06, UMR7588, INSP, F-75005 Paris, France, CNRS, UMR7588, INSP, F-75005 Paris, France; Max-Planck-Institut für Plasmaphysik, Boltzmannstr. 2, 85748 Garching, Germany; imec, Kapeldreef 75, B-3001 Leuven, Belgium; imec, Kapeldreef 75, B-3001 Leuven, Belgium; imec, Kapeldreef 75, B-3001 Leuven, Belgium.

Resume : The continued downscaling of micro and nanoelectronic devices is pursued with the introduction of novel materials (e.g. III-V compounds) and interfaces, frequently with 3D architectures like FinFETs. Hence, there is a growing need for quantitative characterization techniques to probe the composition of layers and narrow features. Traditional approaches using macroscopic analysis methods no longer seem applicable due to the lack of spatial resolution. In this paper, we present the composition analysis of an ensemble of InGaAs fin structures embedded in a SiO2 matrix using complementary transmission electron microscopy (TEM) and Rutherford backscattering spectrometry (RBS). We studied samples containing fins of varying width between 20 nm and 100 nm and 12.5 µm long. We performed Rutherford backscattering measurements using a 1.5 MeV He beam whose spot (0.4 x 0.4 mm2) probes an ensemble of InGaAs fins repeated uniformly and periodically. No attempt is made to perform a local analysis with a nano-focused ion beam, as this would have low accuracy due to counting statistics and may yield non-representative data on an individual outlier device. Rather, the summation over an ensemble of structures leads to statistically relevant data. As RBS signals from different materials appear isolated in the experimental spectrum, we show that it is possible to identify the signal from the fins if those are embedded in a matrix of different, preferably lighter elements. In RBS, not only compositional variations but also variations in the geometry of the fins will have an impact on the detected signals. We used TEM to gain knowledge on the geometry of the fins. The geometrical information obtained from the TEM analysis is used as input in the program StructNRA [1] to analyze the RBS spectra. We prove that the structural information is essential to analyze the RBS spectra. With this work, we demonstrate that it is feasible to use Rutherford backscattering spectrometry to probe the composition of periodic arrays of fins. The reported advancement provides a standardless, quantitative and time efficient tool for the analysis of an ensemble of fins with relevant statistics for process control. Keywords: RBS, hybrid metrology, InGaAs fins. REFERENCE [1] M. Mayer. Nucl. Instr. Meth. B 371 (2016) 90–96.

M.LM.12
12:00
Authors : Georges Beainy(1),(2), Tiphaine Cerba(2), Reynald Alcotte(2), Franck Bassani(2), Mickael Martin(2), Adeline Grenier(1), Thierry Baron(2), Jean-Paul Barnes(1)
Affiliations : (1) Univ. Grenoble Alpes, F-38000 Grenoble, France - CEA, LETI, MINATEC Campus, F-38054 Grenoble, France. (2) Univ. Grenoble Alpes, LTM, F-38000 Grenoble, France and CNRS, LTM, F-38000 Grenoble, France.

Resume : The integration of III-V semiconductor devices on silicon is one of the most challenging topics in current electronic materials research. III-V materials have interesting physical properties, such as a high carrier transport, direct and wide band gap and their integration on silicon will add new functionalities in opto- and micro-electronic applications. However, the integration of III-V on Si faces growth related challenges, i.e. a thermal and lattice mismatches of semiconductors, which affect the device operation. Moreover, given the complexity of the devices in terms of chemical composition as well as in dimension, their accurate characterization has become difficult and sometimes challenging. In this work, the physico-chemical studies of III-V heterostructures directly grown on 300 mm Si wafers by metalorganic vapor phase epitaxy are addressed by the mean of Time of Flight Secondary Ion Mass Spectrometry (ToF-SIMS) and Atom Probe Tomography (APT). These two techniques have emerged as unique that are able to provide information on the chemical composition of elements together with a 3D map indicating the position of each atom from a specimen. Firstly, topography formation under oxygen irradiation of GaSb/InAs multilayers using atomic force microscopy was investigated and correlated with TOF-SIMS profiles in order to improve the depth resolution. Secondly, atomic composition and dopant distribution in Si-doped GaAs thin layers were analyzed by TOF-SIMS and APT and then correlated to the electrical properties.

M.LM.13
12:30 Lunch Break    
 
M-14: Material Characterization and Defects : tba
14:00
Authors : M.H. Zoellner1, G. Chahine2, M.-I. Richard2,3, P. Zaumseil1, M. Häberlen4, G. Capellini1, F. Rovaris5, F. Montalenti5, A. Marzegalli5, P. Storck4, T. U. Schülli2, and T. Schroeder1,6
Affiliations : 1 IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany 2 European Synchrotron Radiation Facility, BP 220, 38043 Grenoble, France 3 Aix-Marseille Université, CNRS, IM2NP UMR 7334, 13397 Marseille, France 4 Siltronic AG, Hans-Seidel-Platz 4, 81737 München, Germany 5 Dipartimento di Scienza dei Materiali, Università degli Studi di Milano-Bicocca, Italy 6 Brandenburgische Technische Universität Cottbus, Konrad -Zuse-Strasse 1, 03046 Cottbus, Germany

Resume : Recent developments of semiconductor heterostructures for modern technologies, as advanced complementary metal-oxide-semiconductor (CMOS) and electronic photonic integrated circuits (EPICs), impose tremendous requirements on the wide variety of metrological methods. Modern synchrotrons are at the very heart of fundamental and applied research due to their increased brilliance and the improvement in focusing X-ray optics. A synchrotron-based scanning X-ray diffraction microscopy technique, called quicK-mapping (K-map), from the beam line ID01 of the European Synchrotron radiation facility (ESRF) is ideally suited for non-destructive and bulk sensitive imaging of local tilt and lattice constant variations with sub-micron resolution.[1] In the presentation, we report about global and local integration schemes of strain engineered Germanium (Ge) on a Silicon (Si) platform. The capability of the K-map technique unveils the crystalline quality in terms of local tilt, strain and composition variation influenced by plastic relaxation in closed Ge/SiGe/Si(001) heterostructures[2,3] and influenced by a top-down structuring process in SiN/Ge/Si(001) microstripes[4]. 1) G.A. Chahine et al. J. Appl. Cryst., 47, 762 (2014). 2) M.H. Zoellner et al. ACS Appl. Mater. Interfaces. Instrum., 7, 9031 (2015). 3) M.-I. Richard et al. ACS Appl. Mater. Interfaces, 7, 26696 (2015). 4) G.A. Chahine et al. Appl. Phys. Lett., 106, 071902 (2015).

M.14.1
14:30
Authors : Jean-Michel Hartmann, Joris Aubin
Affiliations : CEA, LETI, Minatec Campus, F-38054 Grenoble, France & Université Grenoble Alpes, F-38000 Grenoble, France

Resume : Thick Ge layers grown on Si(001) are handy for the production of GeOI wafers, as templates for the epitaxy of III-V and GeSn-based heterostructures and so on. Perfecting their crystalline quality would enable to fabricate suspended Ge micro-bridges with extremely high levels of tensile strain (for mid IR lasers). In this study, we have used a low temperature (400°C) / high temperature (750°C) approach to deposit with GeH4 various thickness Ge layers in the 0.5 µm – 5 µm range. They were submitted afterwards to short duration thermal cycling under H2 (in between 750°C and 890°C) to further reduce the Threading Dislocation Density (TDD). Some of the thickest layers were partly etched at 750°C with gaseous HCl to recover wafer bows compatible with device processing later on. X-Ray Diffraction (XRD) showed that the layers were slightly tensile-strained, with a 104.5-105.5% degree of strain relaxation irrespective of the thickness. The surface was cross-hatched, with an AFM surface roughness slightly decreasing with the thickness, from 2.0 down to 0.8 nm. The TDD (from Omega scans in XRD) decreased from 8E7 cm-2 down to 1E7 cm-2 as the Ge layer thickness increased from 0.5 up to 5 µm. The lack of improvement when growing 5 µm thick layers then etching a fraction of them with HCl over same thickness layers grown in a single run was at variance with Thin Solid Films 520, 3216 (2012) (scant process details in it). HCl defect decoration is underway to confirm our findings.

M.14.2
14:45
Authors : F. Rovaris(1), M.H. Zoellner(2), G.A. Chahine(3), P. Zaumseil(2), P. Storck(4), M. Haeberlen(4), A. Marzegalli(1), T. Schroeder(2), G. Capellini(2), and F. Montalenti(1)
Affiliations : (1) L-N ESS and Dipartimento di Scienza dei Materiali, Università di Milano-Bicocca, Via R. Cozzi 55, 20125 Milano, Italy; (2) IHP, ImTechnologiepark 25, 15236 Frankfurt( Oder), Germany; (3) CNRS, SIMAP, F-38000 Grenoble, France; (4) Siltronic AG, Hans-seidel-Platz 4, 81737 München, Germany.

Resume : Dislocations are defects unavoidably created during deposition of lattice-mismatched films. Controlling their distribution and the density of threading arms reaching the film surface is fundamental for applications, as dislocations can seriously hinder the desired performances of various devices. A detailed, quantitative understanding of their nucleation, subsequent gliding and final distribution is still lacking. One of the main problems stems in the difficulties encountered when attempting to experimentally provide a complete characterization of the defects. Dislocations are characterized by misfit segments (with full or partial edge character), suitably connected to threading arms. The distribution of threading arms at the free surface can be easily analyzed by various techniques. Inner misfit segments, on the other hand, can be imaged only by time-consuming and destructive techniques such as TEM analysis, usually leading to poor statistics. Recent developments in fast-scanning X-rays microscopy have recently opened up the possibility to record detailed tilting-angle maps [1,2], as caused by the dislocation distribution in the film and in the substrate. Here we present a theoretical procedure allowing one to extract from such maps, and from the knowledge of the residual strain R in the film, the position of individual dislocations. Based on the exact (within linear elasticity theory) expression of the tilting angle produced in the crystal by a dislocation, and by fixing the density of misfit segments based on the R value, we generate distributions of dislocations and compare the predicted and measured tilt map. Based on local deviations between simulated and experimental maps, we further change the dislocation distribution until a good match is obtained. To make the procedure efficient we directly exploit the physics of the system: instead of sampling all possible dislocation positions in the simulation cell, we use dislocation dynamics simulations to evolve the system from a starting guess to a local equilibrium position. The procedure is here applied to Ge0.07 Si0.93 films grown on Si(001) by Chemical Vapor Deposition. A thicker (1500nm) and thinner sample (600nm) were grown and the corresponding tilting maps were obtained as in [2]. Our methodology was then applied, leading to interesting results: in both cases the model predicted the occurrence of several identical dislocations piling-up on the same glide plane, and penetrating the Si substrate, a clear indication of the presence of multiplication processes [3]. Interestingly, the number of dislocations not produced by multiplication turned out to be almost constant in both samples, in spite of the different residual strain (as expected, the thicker film is more relaxed). What changes when the film gets thicker, instead, is the number (growing with thickness) of dislocations in isolated pile ups. Based on these results, an interpretative model of relaxation in the samples is built, distinguishing between a first phase, where “standard” dislocations form and glide to the film/substrate interface, and a second where nucleation of additional defects mainly takes place by multiplication, likely produced by crossing and self-blocking between dislocations. The model predictions are further checked by selected TEM images, confirming both the presence of misfit-segments pile ups and of dislocations penetrating the Si substrate. [1] V. Mondiali et al., APL 105, 242103 (2014); [2] M.I. Richard et al., ACS Appl. Mater. & Interfaces 7, 26696 (2015); [3] F.K. LeGoues et al, Phys. Rev. Lett. 66, 2903 (1991).

M.14.3
15:00
Authors : K. Iordanidou1, M. Houssa1, J. Kioseoglou2, V. V. Afanas’ev1, A. Stesmans1
Affiliations : 1Department of Physics and Astronomy, University of Leuven, B-3001 Leuven, Belgium; 2Department of Physics, Aristotle University of Thessaloniki, GR-54124 Thessaloniki, Greece

Resume : Single and few-layer indium selenides are currently attracting intense interest due to their promising applications in future electronic nanodevices. In this work, using first-principles calculations based on density functional theory, we study the structural, energetic and electronic properties of various point defects, in single-layer InSe. Se vacancies and antisites are found to be thermodynamically favorable among all considered imperfections with formation energies 2.19 and 2.39 eV, respectively, and are found to significantly influence the electronic properties by introducing defect levels within the gap. The oxygen and hydroxyl adsorption on pristine and Se/In deficient monolayers is also investigated. Our simulations reveal that single-layer InSe suffers severely from atomic oxidation which results in the formation of Se-O and In-O bonds. In contrast to atomic O adsorption, the interaction of molecular O with InSe is weak and it can only be physisorbed. Interestingly, oxygen adsorption on Se deficient monolayers acts as a passivation mechanism, both “structurally” by saturating the dangling bonds of neighboring metal atoms and “electronically” by removing the Se vacancy induced gap states. In general, our results highlight the importance of controlling defects to achieve good performance in future InSe-based field effect transistors, and also provide new insights into their oxidation.

M.14.4
15:15
Authors : Xuanxiong ZHANG
Affiliations : School of Optical-Electrical and Computer Engineering, University of Shanghai for Science and Technology

Resume : Wafer fusion bonding technology has been used to fabricate SOI material. Researchers are being interested in the integration of III-V and Si in order to gain III-V unique property in conjunction with the matured Si CMOS technology for SOC applications. The III-V is also one of the options as a NMOS channel for the future CMOS or beyond Moore’s law. Therefore, wafer fusion bonding technology combined with layer transfer has been naturally taken into account for the manufacturing engineering substrate owing to contaminant-free. Previous investigations reported a high performance differential amplifier through the direct monolithic integration of InP HBTs and Si CMOS on silicon substrates by a starting stacked engineering wafer and achieved InP/Si wafer-scale bonding by O2-plasma activation and 300C annealing but a great number of vertical outgassing channels (VOCs) patterned prior to wafer bonding have been employed. Moreover, the high defect density at the bonding interface was still in existence due to the lack of optimal InP/Si wafer fusion bonding process and the pictures of interface microstructure taken only by scanning electron microscope (SEM) were shown. In this report, we present a method of the low temperature InP/Si wafer bonding by means of O2-plasma activation to achieve atomic level wafer bonding in the case of an annealing at 300C without any pre-patterned channels on the wafer surface for outgas diffusion. A few tiny voids generated at the bonding interface can be observed by scanning acoustic microscopy (SAM) owing to high resolution to the formed voids although nothing viewed in the image from infrared transmission inspection.

M.14.5

Symposium organizers
Clement MERCKLINGImec

Kapeldreef 75, 3001 Leuven, Belgium

+32 (0)16 28 86 91
clement.merckling@imec.be
Didier LANDRUSOITEC

Parc Technologique des Fontaines – Chemin des Franques - F38190 Bernin - France

+33 4 76 92 94 76
didier.landru@soitec.com
Francesco MONTALENTIUniversity of Milano-Bicocca

Dipartimento di Scienza dei Materiali, Via R. Cozzi 55, 20125 Milan - Italy

+39 0264485226
francesco.montalenti@unimib.it
Inga Anita FISCHERInstitut für Halbleitertechnik, Universität Stuttgart

Pfaffenwaldring 47, 70569 Stuttgart, Germany

+49 711 68568006
fischer@iht.uni-stuttgart.de