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2015 Fall

Materials for electronics and optoelectronic applications away from silicon.

O

Alternative semiconductor integration in Si microelectronics: materials, techniques & app

The symposium aims to gather scientists working on monolithic heterogeneous integration to expand silicon technology. It builds on a series of symposia that attracted a steadily increasing number of attendees. This research paves the way towards highly functionalized Silicon-based microelectronics technologies that can address challenges in our societies.

 

Scope:

 

Silicon is the material of choice for manufacturing integrated circuit (IC), achieving an unbeaten level of system integration. Fundamental physical limits of Si present however major stumbling blocks for miniaturization (“More Moore”) and functionalization (“More than Moore”) of Si-based ICs. In parallel though, new markets driven by societal needs – mobile & low power technologies, ultra-fast data communication, cognitive systems, biomedical application – will stem from technologies where the integration of alternative semiconductors on the mature Si technology platform will be a key differentiator.

The symposium will be devoted to highlight novel breakthrough approaches that impact monolithic heterogeneous integration on silicon CMOS, be it about fundamental materials understanding, using novel integration schemes or targeting new field of application. The focus will be first on basic materials issues related to group IV (graphene, Ge, SiGe, (Si)GeSn etc.); III-V (Arsenides, Phosphides, Antimonides, etc); and x-VI (oxides, nitrides), covering fabrication and characterization. Contributions related to innovative hetero-integration techniques (advanced hetero epitaxy, wafer bonding, microstructure printing etc.) will be encouraged. Finally, a particular attention will be given to applications demanding an interdisciplinary approach, eg cognitive technologies and biomedical or environmental sensors. The productive interaction across disciplines (eg between life science and Si technology) will be critical to exploit the combined power of CMOS enhanced with new materials. It will help materials scientists to drive the exciting transition towards higher-value Si microelectronics, supporting technology that supports society.

 

Hot topics to be covered by the symposium:

 

Materials science, fabrication and characterization:

 

Group IV and IIIV semiconductors:

SiGe, Ge, and (Si)GeSn heterostructures, SOI, GOI, graphene and carbon nanotubes. Arsenides, phosphides, nitrides and antimonides.

Oxides and nitrides:

Functional perovskites, ZnO, GaN and heterostructures, oxides with resistive or metal insulator transition, topological insulators, etc.  

 

Integration Techniques: 

 

Advanced heteroepitaxy:

Epitaxial lateral overgrowth, patterned wafer approaches, self-assembly techniques

Layer Transfer and TSV:

Wafer bonding, microstructure printing, die to wafer etc. Through Silicon Via techniques etc..

 

Applications: 

 

Applications: Logic and data communication:

CMOS, high-power / frequency transistors; IR and THz lasers; modulators, photodetectors, resonators.

New computing paradigm:

Native neuromorphic devices and circuits, quantum computing and communication

Biomedical application and environmental sensors:

Convergence with microfluidics, plasmonics for SERS, gas sensors etc.

 

Tentative list of invited speakers:

 

In order to account for possible changes, the following list include a few additional speakers with respect to the final program that will be proposed

 

  • Jean-Marc Girard (Air Liquide Advanced Materials, USA) «Advanced precursors for semiconductor processing»
  • Kristel Fobelets (Imperial College Londen, UK) «Conductivity and 1/f noise in Si nanowire arrays»
  • Sebastian Koelling (University of Eindhoven, The Netherlands) «Advanced semiconductor characterization using Atom Probe»
  • Cary Gunn (Genalyte, USA) «Silicon based assays for biomarker and protein detection»
  • Isabelle Berbezier (CNRS, France) «Group IV nanostructures»
  • Douglas J. Paul (University of Glasgow, UK) «Silicon based THz systems»
  • Charles Cornet (INSA Rennes, France) «InGaP integration on Si for photonics and energy»
  • Bernd Witzigmann (University of Kassel, Germany) «Computational Physics of Nanowire Photonics Applications»
  • Florencio Sanchez (ICMAB, Spain) «Functional Oxides on Silicon»
  • Martin Kalbac (Uni Prag, Slovakei) «Graphene Research»
  • Julie Grollier (CNRS-Thales, France) «Nanodevices for Cognitive Information Processing»
  • Clement Merckling (IMEC, Belgium) «III-V integration on silicon for CMOS»
  • Sasan Fathpour (University Central Florida, USA) «Heterogeneous Lithium Niobate Photonics on Silicon Substrates»
  • Kristinn B. Gylfason (KTH, Sweden) «Silicon photonics for biosensing applications»
  • Ségolène Olivier (CEA, France) «Hybrid III-V on Silicon Lasers for Photonic Integrated Circuits on Silicon»
  • Stephan Wirths (Forschungszentrum Juelich, Germany) «Lasing from GeSn-based structures»

 

Tentative list of scientific committee members:

 

  • D. Buca, Juelich FZ
  • F. Walker, Yale
  • Y.-H. Xie, UCLA
  • G. Chahine, ESRF
  • R. Erni, EMPA
  • R. Czajka, TU Poznan
  • A. Marzegalli, U Milano
  • S. Takagi, U. Tokyo
  • V. Sverdlov, TU Wien
  • S. Spiga, MDM-CNR
  • P. Davids, Sandia Nlabs
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Symposium O opening : Jean Fompeyrine
08:50
Authors : Jean Fompeyrine (1), Giovanni Capellini (2), Thomas Schroeder (3), Roger Loo (4)
Affiliations : (1) IBM Research GmbH, Zuerich Research Laboratory, Saeumerstrasse 4, CH-8803 Rueschlikon, Switzerland; (2) Dept. of Sciences, Universita Roma Tre, Viale G. Marconi 446, 00146 Roma, Italy; (3) Leibniz Institute for Innovative microelectronics (IHP), Im Technologiepark 25, 15236 Frankfurt (Oder), Germany; (4) Imec, Kapeldreef 75, B - 3001 Leuven, Belgium

Resume : Opening remarks

O.0.1
 
Nanostructures 0D : Jean Fompeyrine
09:00
Authors : Thomas David, Luc Favre, Kailang Liu, Jean-Noel Aqua, Abdelmalek Benkouider, Meher Naffouti, Marco Abbarchi, Antoine Ronda, Martiane Cabié, Thomas Nelsius, Isabelle Berbezier
Affiliations : /

Resume : The fabrication of ultra-thin Ge-rich SiGe body on Silicon On Insulator (SOI) is highly challenging for the next generation of fully depleted CMOS devices that will be implemented in microelectronic industry. Ge-rich layers (GRLs) could be fabricated using a Ge enrichment process which takes place during dry thermal oxidation of SiGe thin films. While several studies make use of the GRL for many applications, the basic mechanism at work during the enrichment process is still unclear. In this study, we address the mechanism of formation of the GRL in two different situations and we determine the major driving forces of the enrichment process. The enrichment process is examined for different strain states: a fully relaxed Si1-xGex (x=0.2) buffer layer and a strained epitaxial Si1-xGex (x=0.2) film on SOI. For the two samples, the GRLs have the same concentration x=0.5 whatever the experimental conditions and the nominal strain state are. With this systematic study, we demonstrate that the 50% Ge content is stabilised by a self-limited segregation-like process regulated by the entropic term of the formation energy which is minimum at Si0.5Ge0.5 at the expense of the elasticity driven interdiffusion. We highlight the particular role played by this 50% concentration which is stabilized up to temperatures ≤900°C. The process provides an easy and efficient way to produce planar GRLs free of dislocations with abrupt SiGe/Si interfaces and tunable thickness. These GRLs could be fashioned for the heterogeneous integration of various systems on SOI. We demonstrate the use of the process for two typical examples of SiGe/Si core-shell systems: nanowires and nanocrystals.

O.1.1
09:30
Authors : M. Grydlik, F. Hackl, H. Groiss, T. Fromherz, W. Jantsch, F. Schäffler and M. Brehm
Affiliations : Institute of Semiconductor and Solid State Physics, Johannes Kepler University Linz, Altenbergerstrasse 69, 4040 Linz, Austria

Resume : Silicon-based light emitters, compatible with the existing integrated technology became of high interest to overcome limitations in the operating speed of microelectronic devices. The bottleneck in the performance of group-IV element light emitters is based on the poor optical properties of bulk Si and Ge. Here, we demonstrate that epitaxially grown Ge quantum dots, partially amorphized due to Ge ion-bombardment (GIB), can be embedded into a coherent crystalline Si matrix as shown by transmission electron microscopy experiments. These hybrid amorphous/crystalline GIB-Ge-dots exhibit in contrast to conventional coherent SiGe nanostructures a very high activation energy for thermal quenching and, consequently, superior PL properties at room temperature. The integrated PL-emission from the QDs is not even reduced by a factor of two by increasing the sample temperature from 6 K to 300 K. Due to their small size and additional strong electron localization at dangling bond states in the amorphous part of the GIB-QDs, the energy bandgap of the GIB-QDs is quasi-direct. Spatially, the radiative transitions are of type-II for low excitation powers and of type-I for excited states. Therefore, the lifetimes of the carrier recombination processes in the GIB-QDs are very fast, of about 1 ns and stimulated emission from GIB-QDs in a microdisk was demonstrated. The GIB-QDs can be easily manufactured as they are grown directly on Si without the need of thick dislocated graded-buffer layers.

O.1.2
09:45
Authors : Gang Niu1*, Giovanni Capellini1,2, Tore Niermann3, Marco Salvalaglio4, Anna Marzegalli4, Markus Andreas Schubert1, Peter Zaumseil1, Hans-Michael Krause1, Oliver Skibitzki1, Michael Lehmann3, Francesco Montalenti4, Ya-Hong Xie5, Thomas Schroeder1,6
Affiliations : 1 IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany 2 Dipartimento di Scienze, University Roma Tre, Viale Marconi 446, 00146 Rome, Italy 3 Technische Universitaet Berlin, Institut fuer Optik und Atomare Physik, Strasse des 17. Juni 135, 10623 Berlin, Germany 4 L-NESS and Dept. of Materials Science, University degli Studi di Milano-Bicocca, via Cozzi 55, Milan, Italy 5 University of California at Los Angeles, Department of Materials Science and Engineering, Los Angeles, CA 90095-1595, USA 6 BTU Cottbus-Senftenberg, Konrad-Zuse-Str.1, 03046 Cottbus, Germany

Resume : High quality Ge nano-islands on silicon are very attractive for both electronic and optoelectronic devices. In this report, we demonstrate wafer-scale integration of relaxed Ge islands on up to 4 inch size Si (001) substrate via Si nano-tips. The Si-tip patterned substrate, fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology, features ~50 nm wide Si areas emerging from a SiO2 matrix and arranged in an ordered lattice. Molecular beam epitaxy (MBE) growths result in Ge nano-islands with high selectivity and having homogeneous shape and size. The mechanism of pattern-independent selectivity will be discussed in detail. The ~850?C growth temperature required for ensuring selective growth has been shown to lead to the formation of Ge islands of high crystalline quality without extensive Si intermixing (with 91 at.% Ge). Nano-tip patterned wafers result in geometric intermixing hindrance confining the major intermixing to the pedestal region of Ge islands. Theoretical calculations suggest that the thin SiGe layer at the interface plays a significant role in realizing the fully coherent Ge nano-islands free from extended defects especially dislocations. Such well-ordered Ge-rich islands with low defect density could certainly help to improve the performance of Ge based nano-devices.

O.1.3
10:00
Authors : T. Grzela(1), G. Capellini(1), T. Schroeder(1), I.Heidemann(2), Th. Schmidt(2), J.Falta(2) and W. M. Klesse(1)
Affiliations : (1) IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany (2) Institute of Solid State Physics, University of Bremen, Otto-Hahn-Allee 1, 28359 Bremen, Germany

Resume : Germanium (Ge) and germanium-tin (GeSn) alloys have emerged as strong alternatives to silicon in post-silicon computing, owing to their superior optoelectronic properties and compatibility with conventional transistor technology. However, the ultimate success of future Ge- and GeSn technologies, such as high-current Ge-based MOSFETs or lasers, are critically linked to the development of low-resistance and thermally stable Ohmic contacts. Here, among other metal systems, nickel germanide (NiGe) has attracted significant attention, due to its relatively low electrical resistivity and low formation temperature. In this context, we present a multi-technique experimental study on the underlying physical/chemical mechanism of Ni germanide formation. By combining STM measurements with LEEM, LEED, (S)TEM-EDX and XPS we studied at the atomic level the growth and evolution of NixGey nanostructures on Ge(001). By carefully tuning the experimental parameters we compared different deposition coverages, substrate temperatures and post-anneal treatments. Starting at relatively low temperatures of 100°C we observed the formation of a continuous NixGey wetting layer, which gradually evolves to well-ordered NixGey 3D nanostructures with increasing temperature. Finally, motivated by the well-known high sensitivity of NixGey formation to impurities and defects at the Ge/Ni interface, we explored the impact of surface-stain and incorporated Sn-atoms on the nucleation of NixGey on Ge(001).

O.1.4
10:15
Authors : Ryoma Hayakawa *1, Kenji Higashiguchi 2,3, Kenji Matsuda 2, Toyohiro Chikyow 1 and Yutaka Wakayama 1
Affiliations : 1. International Center for Materials Nanoarchitechtonics (WPI-MANA), National Institute for Materials Science, 1-1 Namiki, Tsukuba 305-0044, Japan 2. Department of Synthetic Chemistry and Biological Chemistry, Graduate School of Engineering, Kyoto University, Katsura, Nishikyo-ku, Kyoto 615-8510, Japan 3. PRESTO, Japan Science and Technology Agency, Kawaguchi 332-0012, Japan

Resume : Single molecular devices have been promising candidates for future CMOS devices. However, the development of such molecular devices is still at the basic research stage and practical application remains a long way off. We have proposed the adoption of functional organic molecules as quantum dots in a metal-oxide-insulator (MOS) structure to integrate attractive molecular functions into current Si devices. In this presentation, we demonstrate multi-functional manipulations of carrier transports through molecules in the Si-based double tunnel junction. First, we observed resonant tunneling through various kinds of molecules. In particular, in the sample with C60, the tunneling was observed even at 280 ºC which is almost room temperature.[1] These results show that the carrier transports via molecular dots can be controlled by molecular orbitals. As an example, we attained multilevel control of resonant tunneling by employing binary molecules of CuPc and F16CuPc.[2] Furthermore, the adoption of diarylethene photochromic molecules enabled reversible optical switching in the resonant tunneling.[3] These results are unique features to use molecules as quantum dots, which will allow the integration of attractive molecular functions into current CMOS devices. [1] R. Hayakawa et al., Adv. Funct. Mater. 21, 2933-2937 (2011). [2] H.-S. Seo, R. Hayakawa et al., J. Phys. Chem. C vol. 118, pp. 6467-6472 (2014). [3] R. Hayakawa et al., ACS Appl. Matter. Interfaces 5, 11371 (2013).

O.1.5
10:30 Cofee break    
 
Nanostructures 1D I : Sebastian Koelling
11:00
Authors : Bernd Witzigmann
Affiliations : Computational Electronics and Photonics Group, and CINSaT, University of Kassel, Wilhelmshöher Allee 71, 34121 Kassel, Germany

Resume : High quality III-V nanowires can be grown on Silicon substrates. In this presentation, the physical principles of semiconductor nanowire arrays are discussed, with a focus on photovoltaics and solid state lighting. As analysis tools, specific physics-based numerical models for nanophotonics and nanoelectronics have been developed, which will be discussed. In particular, the three-dimensional nature of a wire array, including the substrate and the free space on top is included in the study. For the optical extraction efficiency of an LED, absorption of electromagnetic energy in the contacts and the active layers themselves, as well as re-emission (photon-recycling) are investigated. The latter is an effect that couples the electronic and the optical system. In addition, the optical density of states is analyzed and its impact on the extraction efficiency is shown. Finally, the total electro-optical efficiency of a nanowire array LED is presented and compared to state of the art thin-film LEDs. For the nanowire array solar cell, a detailed electromagnetic and electronic analysis is presented, from which fundamental rules in terms of materials choice and wire geometry will be derived. It shows that low density regular III-V nanowire arrays can reach absorptivities identical to bulk cells, with the advantage of substrate flexibility, low material consumption, and strain engineering for multi-junction cells. As outlook, III-nitride nanowire photovoltaics is discussed.

O.2.1.1
11:30
Authors : Ivano Giuntoni (1), Lutz Geelhaar (1), Jürgen Bruns (2), Klaus Petermann (2), Henning Riechert (1)
Affiliations : (1) Paul-Drude-Institut für Festkörperelektronik, Hausvogteiplatz 5-7, D-10117 Berlin, Germany (2) Technische Universität Berlin, Fachgebiet Hochfrequenztechnik, Einsteinufer 25, D-10587 Berlin, Germany

Resume : Silicon photonics is a powerful and flexible platform for the realization of compact and low-cost optoelectronic devices which could enable overcoming the bottleneck in bandwidth of electrical on-chip and chip-to-chip interconnects. However, for some key applications like light generation silicon has to be combined with III-V semiconductors exhibiting direct bandgaps. The mismatch in lattice constants can be mitigated if these materials are grown in form of vertical free-standing nanowires, since in this case strain can elastically relax at the sidewalls. We present a new concept for the optical interfacing between vertical nanowires and planar silicon waveguides based on the selective growth of nanowires which form a grating structure on top of a silicon waveguide. This grating ensures light coupling between planar silicon structures and upright standing III-V nanowires. Numerical simulations show this technique permits a light extraction from the waveguide larger than 50%. Our new integration approach allows at the same time the electrical operation of devices based on these nanowires. Potentially very fast photodiodes could be achieved, if a pn junction is implemented in the nanowires. More importantly, the proposed system can be considered as the first step towards the integration of light sources. Our concept could hence pave the way to on-chip optical interconnect systems comprising Si waveguides and III-V nanowire lasers as well as photodiodes.

O.2.1.2
11:45
Authors : I. A. Fischer, L. Augel, S. Jitpakdeebodin, T. Kropp, N. Franz, S. Fleischer, J. Schulze
Affiliations : Institute for Semiconductor Engineering, University of Stuttgart, Paffenwaldring 47, 70569 Stuttgart

Resume : Plasmonic nanoantennas are metallic nanostructures that enable the control and manipulation of optical energy in the visible and near-infrared spectrum and have been proposed as a means to enhance absorption and quantum yields for photovoltaics, for local-surface-plasmon-resonance-based biosensors and to enhance the energy efficiency of light-emitting devices. Here, we present experimental results on the enhancement of Ge PIN-photodetector efficiency by Al nanoantennas in a Complementary-Metal-Oxide-Semiconductor-compatible setup. We fabricated disk- and rod-shaped Al nanoantennas by means of electron-beam lithography and incorporated them into the passivation layer of Ge PIN-photodetectors. Under vertical illumination the influence of the nanoantennas can be seen in a wavelength-dependent increase in photocurrent that is most pronounced close to the absorption edge of Ge. We discuss the physical origins of this effect as well as how such structures can serve as a base for plasmonic biosensing applications integrated on chip.

O.2.1.3
12:00 Lunch break    
 
Nanostructures 1D II : Isabelle Berbezier
14:00
Authors : 1. Kristel Fobelets
Affiliations : Department of Electrical and Electronic Engineering, Imperial College London, London, UK

Resume : Gas molecule must adsorb on the surface of the device which can be enhanced by defects in the system. The activity of these can be measured via low frequency noise, which is very sensitive to changes in the surface states. We have applied this technique to n and p type silicon nanowire arrays (NWAs) and have demonstrated that low frequency noise can be used as an additional parameter to measure NH3 and NO2 selectively in the presence of water vapour. The interaction of NH3 and NO2 with the surface of core/shell Si/SiO2 NWs influences their electrical conductivity because NH3 and NO2 are electron and hole donors, resp. Using arrays of n- and p-type Si nanowires, we demonstrate that their influence on the low frequency noise characteristics of the NWs is largest when the donors are minority carriers. The impact of NO2 and NH3 on 1/f noise of p- and n-type NWs, respectively, is limited. However, 1/f noise increases in n-Si NWs under influence of NO2 while it decreases in p-Si NWs for NH3. This effect is attributed to oxygen vacancies in the SiO2 and the presence or absence of holes, h+ in a humid gas environment. In addition, gas molecule adsorption in a humid atmosphere, influences the pH and thus the surface charge density on the SiO2 shell, causing changes in the low frequency noise level via electrostatic interactions. In this presentation we will give an overview of the state-of-the art and the use of Si NWs for the detection of NO2 and NH3 in a humid environment.

O.2.2.1
14:30
Authors : Grace Flynn, Quentin M. Ramasse, Kevin M. Ryan
Affiliations : Materials and Surface Science Institute and Department of Chemical and Environmental Sciences, University of Limerick, Limerick, Ireland; SuperSTEM Laboratory, SciTech Daresbury Campus, Daresbury WA4 4AD, United Kingdom

Resume : Silicon (Si) and germanium (Ge) nanowires (NWs) are very promising materials for their use in applications such as energy storage, transistors and photovoltaics. Compound semiconductor NWs are of particular interest for their potential use in high performance devices such as field effect transistors. Herein, we present the high density growth of multi-segment axial Si-Ge heterostructure NWs in a versatile, low cost glassware system, where the vapour phase of a high boiling point solvent acts as the growth medium. A variety of heterostructure NW combinations can be grown using this system, including Si-Ge, Ge-Si, Si-Ge-Si, Ge-Si-Ge as well as double and triple Si-Ge, with minimal alloying observed at the Si-Ge interfaces. An evaporated layer of tin (Sn), on stainless steel was chosen as the growth substrate. Sn was chosen as it is a low solubility type B catalyst which allows for the production of highly abrupt interfaces between the Si and Ge segments. The length of each Si and Ge segment can also be controlled in this system by carefully controlling the reaction time. These NWs are characterised using high resolution transmission electron microscopy (HRTEM), dark field scanning transmission electron microscopy (DF-STEM) and energy dispersive X-ray analysis (EDX), with aberration corrected scanning transmission electron microscopy allowing for determination of the interfacial abruptness between the Si and Ge segments.

O.2.2.2
14:45
Authors : Jann E. Kruse12, Savvas Eftychis1, Adam Adikimenakis2, George Doundoulakis12, Katerina Tsagaraki2, Maria Androulidaki2, Antonis Olziersky3, Panagiotis Dimitrakis3, Vassilios Ioannou-Sougleridis3, Pascal Normand3, Triantafyllia Koukoula4, Thomas Kehagias4, Philomela Komninou4, Alexandros Georgakilas1
Affiliations : 1 Department of Physics, University of Crete, 71003 Heraklion, Greece; 2 Microelectronics Research Group, IESL, FORTH, 71110 Heraklion, Greece; 3 Department of Microelectronics, NCSR Demokritos, 15310 Aghia Paraskevi, Greece; 4 Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece

Resume : We demonstrate and analyse a method to grow straight, vertical GaN nanowires by plasma-assisted MBE at sites specified by a SiO2 mask, which was grown thermally into the Si(111) substrate and patterned by electron-beam lithography. We present an analytic study involving various mask patterns and a variety of characterization techniques to observe how the dimensions of the mask affect the morphology of the nanowires, their distribution and alignment as well as their photonic properties. The capabilities and limitations for the selective-area growth (SAG) of nanowires on SiO2-patterned Si(111) have been identified. Using matching mask and growth parameters, we were able to grow regulararrays of straight, vertical nanowires, at sites specified by the mask, with almost no growth on the mask itself, yielding a near 100% selectivity. One advantage of this method is the use of standard Si substrates without the need for any buffer layer. This results in a significantly simpler and faster process and likely in lower cost. Since the substrate itself is used as mask simply by oxidization, it is not needed to deposit additional mask material, except the electronresist, which may integrate well with Si processing techniques in many laboratories. However, the results indicate a limited range of mask window diameters and spacings, which result in successful nucleation and growth of straight, vertical nanowires. This work was co-financed by EU (ESF) and Greek funds. Program: THALES

O.2.2.3
15:00
Authors : A. Carretero-Genevrier1, Judith Oró-Solé 2, Jaume Gázquez 2, Teresa Puig 2, Xavier Obradors2, Clément Sanchez3, Etienne Ferain4, Juan Rodríguez-Carvajal5, Narcís Mestres2*
Affiliations : 1 Institut des Nanotechnologies de Lyon (INL) CNRS, 36 avenue Guy de Collongue, 69134 Ecully, France; 2 Institut de Ciència de Materials de Barcelona ICMAB-CSIC, Campus UAB 08193 Bellaterra, Spain; 3 Laboratoire Chimie de la Matière Condensée, UMR UPMC-Collège de France-CNRS 7574. Collège de France, 11 place Marcelin Berthelot, 75231 Paris, France; 4 it4ip sa, 1 avenue Jean-Etienne Lenoir, 1348 Louvain-la-Neuve, Belgium; 5 Institut Laue-Langevin, 6 rue Jules Horowitz, BP 156, 38042 Grenoble Cedex 9, France

Resume : Monolithic direct integration of functional oxide nanowires with vertically oriented crystals on a semiconductor platform is challenging due to difficulties on preserving epitaxy, crystalline phase, and composition. Here, we developed a new strategy to produce vertical epitaxial single crystalline manganese oxide based nanowires thin films with tunable composition and enhanced ferromagnetic properties on Si substrates by using a chemical solution deposition approach [1]. The nanowire growth mechanism involves the use of track-etched nanoporous polymer templates combined with the controlled growth of quartz thin films at the Si surface, which allowed the epitaxial stabilization and crystallization of the oxide nanowires. α-quartz layers were obtained by thermally activated devitrification of the native amorphous silica surface layer assisted by a heterogeneous catalysis driven by alkaline earth cations (Sr2+, Ba2+ or Ca2+) present in the precursor solution [2]. Therefore, the combination of soft-chemistry and epitaxial growth opens new opportunities for the effective integration of novel technological functional complex oxides nanomaterials on Si substrates [3]. References [1] A. Carretero-Genevrier et al. Chem.Soc.Rev. 43, 2042 (2014) [2] A. Carretero-Genevrier et al. Science 340, 827 (2013) [3] A. Carretero-Genevrier et al. Chem. Mater. 26, 1019 (2014)

O.2.2.4
15:15
Authors : Thomas DEMES, Céline TERNON, Michel LANGLET, Valérie STAMBOULI
Affiliations : Univ. Grenoble Alpes, LMGP, F-38000 Grenoble, France

Resume : Randomly oriented nanowire (NW) networks, also called nanonets, represent promising nanostructures due to their high surface to volume ratio, their easy integration, as well as their simple, inexpensive and scalable production. Particularly, semiconducting nanonets are highly attractive regarding a wide variety of applications such as light-, gas- or bio-sensing devices. In this work, ZnO nanonets are investigated with the aim of developing electrical DNA biosensors. These biosensors, which have various application fields, ranging from medical diagnostic to forensics, should enable to perform portable and low-cost devices for direct, fast and label-free DNA detection. This work presents the different ZnO nanonet fabrication steps, starting from chemical precursors, and their subsequent integration into electrical DNA biosensors: (1) ZnO seed layer deposition on silicon substrates by sol-gel approach; (2) ZnO NW growth by hydrothermal synthesis; (3) ZnO nanonet assembly into percolating 2D random networks; (4) DNA biosensor integration and characterization. High aspect ratio (>50) NWs with diameter less than 50nm are expected for nanonet assembling and maximal sensitivity when exposed to biomolecules. In this view, a particular attention is given to the first fabrication steps until nanonet assembling to demonstrate how we succeeded in controlling precisely the NW diameter (from 20 to 200nm) and aspect ratio (from 10 to 200). First results concerning bio-sensing are also shown.

O.2.2.5
15:30 Coffee break    
 
Nanostructures 2D : Bernd Witzigmann
16:00
Authors : Martin Kalbac1,2 Johan Ek Weis,1 Sara Costa,1 Jana Vejpravova,3 P.T. Araujo, 2 W. Fang, 2 Jing Kong, 2 and Mildred S. Dresselhaus 2,4
Affiliations : 1 J. Heyrovský Institute of Physical Chemistry, Academy of Sciences of the Czech Republic, v.v.i., Dolejškova 3, CZ-18223 Prague 8, Czech Republic. Tel: 420 2 6605 3804; Fax: 420 2 8658 2307; E-mail: kalbac@jh-inst.cas.cz 2 Department of Electrical Engineering and Computer Science, MIT, Cambridge, Massachusetts 02139, USA 3 Institute of Physics, Academy of Sciences of the Czech Republic, v.v.i., Na Slovance 2, Czech Republic. 4 Department of Materials Science and Engineering, MIT, Cambridge, Massachusetts 02139, USA

Resume : Graphene is a fascinating material, which inspired many fundamental and applied research studies. Recently more complex structures based on graphene or other 2-D materials are developed. These engineered layered systems can exhibit new and tunable properties and thus they can lead to significant advances in nanotechnology. One of the major obstacles in the studies of multilayered graphene systems is a difficulty to address the properties of individual layers of such a structure. The Raman spectroscopy is very efficient tool to study graphene and graphene based heterostructures since it provides a lot of information about doping, strain or defects in graphene. Recent advances in the growth of graphene by chemical vapor deposition allowed to prepare isotopically labeled graphene using 12CH4 and 13CH4 precursor gases. Isotopically labeled multilayer graphene can be prepared either by a subsequent transfer of single layer graphene sheets with different content of 13C isotope on top of each other or by direct growth under specific conditions. The direct growth of isotopically labeled two layer graphene also allows to obtain AB stacked layers. The 13C graphene exhibit different positions of its Raman bands due to the higher mass of 13C isotope. Hence, the multilayered graphene systems composed of graphene layers with a different content of 13C isotope can be easily distinguished and addressed in the Raman spectra. In this paper we compare isotopically labeled turbostratic and AB stacked two layered graphene samples and we will review our results obtained on : 1) analysis of the chemical modification of two layer graphene, 2) the effects of the heat treatment on the top and bottom graphene layer of two layered graphene 3) analysis of the effects of electrochemical doping on two layered graphene. References: [1] M. Kalbac,A. Reina-Cecco, H. Farhat, J. Kong, L. Kavan, and M. S. Dresselhaus , ACS Nano, 4 (2010), 6055-6063. [2] M. Kalbac, H. Farhat, J. Kong, P. Janda, L. Kavan, and M. S. Dresselhaus, Nanoletters, 11(2011),1957-1963. [3] M. Kalbac, O. Frank, J. Kong, J. D. Sanchez-Yamagishi, K. Watanabe, T. Taniguchi, P. Jarillo-Herrero, M. S. Dresselhaus. , J. Phys. Chem. Lett. 3, (2012) 796-799. [4] M. Kalbac, J. Kong., M. S. Dresselhaus., J. Phys. Chem. C, 116 (2012), 19046–19050. [5] Wenjing Fang, Allen L. Hsu, Roman Caudillo, Yi Song, A. Glen Birdwell, Eugene Zakar, Martin Kalbac, Madan Dubey, Tomás Palacios, Millie S. Dresselhaus, Paulo T. Araujo, and Jing Kong: Nano Lett., 13 (4),1541–1548 (2013). [6] Paulo T. Araujo, Otakar Frank, Daniela L. Mafra, Wenjing Fang, Jing Kong, Mildred S. Dresselhaus and Martin Kalbac: SCIENTIFIC REPORTS | 3 : 2061 | DOI: 10.1038/srep02061 (2013). [7] Johan Ek-Weis, Sara Costa, Otakar Frank and Martin Kalbac*: J. Phys. Chem. Lett. 5 (3), 549–554 (2014).

O.3.1
16:30
Authors : Gunther Lippert(1), Jarek Dabrowski(1), Tim Schaffus(1), Maria Carmen Asensio(4), Jose Avila(4), Jens Baringhaus(3), Ivy Colambo(5), Felix Herziger(2), Janina Maultzsch(2), Thomas Schroeder(1), Malgorzata Sowinska(1), Christoph Tegenkamp(3), Grzegorz Lupina(1)
Affiliations : (1) IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany (2) Institut für Festkörperphysik, Technische Universität Berlin, Hardenbergstr. 36, 10623 Berlin, Germany (3) Institut für Festkörperphysik, Leibniz Universität Hannover, Appelstr. 2, 30167 Hannover, Germany (4)Synchrotron SOLEIL, Saint Aubin, BP 48, 91192 Gif-sur-Yvette, France (5) I.E.M.N. – Epitaxie, Av. Poincaré, BP 60069, 59652 Villeneuve d'Ascq Cedex, FRANCE

Resume : The common transfer of graphene onto a suitable substrate inherits most likely impurities and defects from the host or transfer process (1). A graphene direct growth method within the device processing line is thus desirable. For example, sublimation of Si out of SiC to synthesize graphene is suitable for SiC platforms but needs too high temperatures for Si technologies (2). The latter technology platform is, however, of central importance for mass market applications. Germanium layers on Si(001) can be covered with graphene (3) to be compatible with the mainstream Si technology requirements. The presentation will show graphene growth on Germanium covered Silicon substrates by simulations (based on supercomputer) and experiments (MBE as well as UHV-CVD). The grown graphene films were characterized by a multi-technique thin film approach including Raman, synchrotron XPS/UPS, AFM, TEM to characterize structural properties (4) Furthermore, the electrical behavior was analyzed by 4probe-STM. 1. G. Lupina et al., Residual Metallic Contamination of Transferred Chemical Vapor Deposited Graphene. ACS Nano 9, 4776 (2015/05/26, 2015). 2. E. Moreau et al., Graphene growth by molecular beam epitaxy on the carbon-face of SiC. Applied Physics Letters 97, 241907 (2010). 3. M. L. I. Pasternak, Y. Yamamoto, A. Krajewska, G. Lupina and W. Strupinski, Optimized graphene growth on Ge(100)/Si(100) substrates. "Graphene 2015" Bilbao, (2015). 4.G. Lippert et al., Graphene grown on Germanium from atomic source. Carbon 75, 104 (2014).

O.3.2
16:45
Authors : E. N. Jin1, L. Kornblum1, D. Kumah1, C. H. Ahn1,2, and F. J. Walker1
Affiliations : 1 Center for Research on Interface Structures and Phenomena, Department of Applied Physics, Yale University, New Haven, Connecticut 06511, USA 2 Department of Mechanical Engineering and Materials Science, Yale University, New Haven, Connecticut 06511, USA

Resume : The development of single crystalline SrTiO3 growth on silicon has opened up many avenues for integrating the multifunctionalities of oxide systems with conventional semiconductor technology. In recent years, it has been shown that a 2-dimensional electron gas (2DEG) forms at certain RTiO3/SrTiO3 interfaces, where R is a trivalent rare earth atom. We present the growth of LaTiO3/SrTiO3 and GdTiO3/SrTiO3 on Si by molecular beam epitaxy, and measure electrical and structural properties. We show in both systems a high density of charge localized at the oxide interface ranging from of ~9 x 1013 cm-2 to ~9 x 1014 cm-2 per interface for the GdTiO3 and LaTiO3 systems, respectively. We also present an approach to use band offset engineering at the SrTiO3-Si interface to move the high carrier density from the oxide into the silicon.

O.3.3
17:00
Authors : S. Koelling (1), A. Li (1,2), H.I.T. Hauge (1), A. Cavalli (1), E.P.A.M. Bakkers (1,2), P.M. Koenraad (1)
Affiliations : 1) Photonics and Semiconductor Nanophysics, TU Eindhoven Postbus 513, 5600 MB Eindhoven 2) Quantum Transport Group, Kavli Institute, TU Delft, Postbus 5046, 2600 GA Delft

Resume : Controlling the assembly of materials on the atomic scale has become an everyday challenge in the electronics industry as the manufacturing process of modern day nanometer-scale devices relies on controlling the deposition and structuring of materials on the atomic-scale in all three dimensions. In order to optimize the properties of these devices it is vital to have a grasp on the atomic arrangement in the fabricated devices. Here we will demonstrate that we can use evaporation of single atoms induced by an electric field to disassemble nano-devices atom by atom. Analyzing the field evaporated atoms makes it possible to create a three-dimensional tomographic mapping including the approximate positions and the chemical identities of the atomic constituents in the disassembled structure. This technique, known as Atom Probe Tomography, enables us to identify and map atoms in nano-devices and nano-structured materials. Here we will show that we can create three-dimensional mappings of the atomic constituents in a wide range of semiconductor devices including CMOS-transistor, quantum dots and nanowires allowing us amongst others to map dopant and contaminant profiles, interface roughness and matrix compositions on a (sub-)nanometer scale.

O.3.4
 
Poster Session : J. Fompeyrine, G. Capellini, R. Loo, T. Schroeder
18:00
Authors : A. Benfdila°, A; Lakhlef
Affiliations : Micro and Nanoelectronics Research Group (MNRG), Faculty of Electrical Engineering and Computer Sciences; University M. Mammeri BP 17 RP Tizi-Ouzou, Algeria °Senior Associate, ICTP-UNESCO-IAEA, Trieste, Italy Email: benfdila@mail.ummto.dz; abenfdil@ictp.it

Resume : The present paper deals with the graphene nanotransistor both operation and fabrication principles aiming a future use as GIC (Graphene Integrated Circuits). The transport model based essentially on the ballistic transport using the Fermi level variations is presented. The switching mechanisms and the threshold voltage limits is discussed to reduce the switching time and ON / OFF states reliability. Finally an overview of the Device processing as well as the integration is discussed using the known VLSI Tools. Difficulties in device engineering as well as process are encountered; however, it is time to speak about graphene integrated circuits.

O.O.1
18:00
Authors : T. Molière1,2, C. Renard1, N. Cherkashin3, A. Jaffré2, L. Vincent1, J. Alvarez2, D. Mencaraglia2
Affiliations : 1 IEF, CNRS-UMR 8622, Bat 220, Univ Paris-Sud, 91405 Orsay, France 2 GeePs, CNRS -UMR 8507, 11 rue Joliot Curie, 91192 Gif-sur-Yvette, France 3 CEMES, CNRS- UPR 8011, Université de Toulouse, 29 rue J. Marvig, 31055 Toulouse, France

Resume : Several technical solutions for GaAs monolithic heteroepitaxy on silicon have been studied for more than 30 years. As for example, the use of buffer layers or structured silicon substrate to localized integration. But until now, no large scale and effective process was found to efficiently reduce the dislocation density down to 104-105cm-2 required for CMOS technology. In order to overcome this difficulty, we propose an interesting concept that permits the heteroepitaxy of mismatched III-V compounds on Si substrate without any substantial mechanical stress and free of any defect. This concept is based on the so-called Epitaxial Lateral Overgrowth (ELO) from nano- apertures through an ultra-thin silicon oxide by CBE. This technique allowed us to obtain perfectly integrated and defect free GaAs microcrystals onto Si as the nucleation from small width openings enables to avoid the emission of misfit dislocations and the formation of antiphase domains. First, we will present our results based on the growth of randomly distributed GaAs microcrystals. Then we will present the nano-technological process allowing us to obtain large organized pattern of nano-sized (20nm) apertures through a thickness controlled oxide, and the associated GaAs microcrystals obtained by ELO. Finally, the results of the GaAs growth in these nano-structured substrates and the structural and electrical characterizations performed by µ-PL, EBIC, CP-AFM and TAP will be discussed.

O.O.2
18:00
Authors : Aoi Tokiwa1, Keisuke Sato1, Naoki Fukata2, Kenji Hirakuri1
Affiliations : 1.Tokyo Denki University; 2.National Institute for Materials Science

Resume : Fluorescent ammonium hexafluorosilicate ((NH4)2SiF6) particles have gained attention as novel fluorescent materials, because of excellent features such as high-efficiency fluorescence and robust photostability. We have developed a new chemical approach with fruitful advantages for synthesis process of such particles. However, the obtained particles exhibit a poor property for fluorescent color, because of yellowish ocher-emission. To tune the fluorescent color, we conducted the phosphorus (P) doping into (NH4)2SiF6 particles. In this presentation, we propose a new way to fabricate the multicolor fluorescent P-doped particles. We adopted a simplified synthesis system in which only Si and P powders and nitric hydrofluoric acid solution were hermetically sealed in polymeric container. The particles having a mean diameter of approximately 1 μm were composed of (NH4)2SiF6/phosphorus oxide composites. The fluorescent color from such particles strongly depended on the P contents. The particles with P content of 0.14 at.% showed bright orange fluorescence with a peak wavelength at 610 nm under the irradiation of 365 nm-xenon lamp. As the P content in particles was increased to 1.02 at.%, the fluorescent color changed to red-light at 640 nm. Hence, our synthesis methods can provide a new chemical route for preparation of multicolor fluorescent particles. This work was partly supported by JSPS KAKENHI Grant Number 26390105.

O.O.3
18:00
Authors : Andriy Hikavyy1, Roger Loo1, Jianwu Sun1;2, Yosuke Shimura1;3;4, Hugo Bender1, Matty Caymax1, and Aaron Thean1
Affiliations : 1 Imec, Kapeldreef 75, B - 3001 Leuven, Belgium; 2 Currently at The Department of Physics, Chemistry and Biology (IFM), Linköping University, Linköping 58183, Sweden; 3 Instituut voor Kern- en Stralingsfysica, KU Leuven, 3001 Leuven, Belgium; 4 FWO Pegasus Marie Curie Fellow

Resume : With continuing scaling, MOS device complexity increases and novel channel materials like epitaxial Ge are being considered. Recently, we described the issue of Ge thermal instability against surface migration during epitaxial Ge growth by CVD in extremely narrow channels isolated by SiO2. Above a critical growth temperature filling of narrow channels is prohibited by Ge surface migration. The Ge thermal instability depends on the channel width and a critical width of 50 nm has been extracted both theoretically and experimentally. During epitaxial Ge growth at a temperature below 450 ?C and using GeH4 as Ge precursor, Ge surface migration is retarded by the hydride-termination on the surface, providing excellent channel filling. However, this low temperature Ge growth results in twin defect formation at the vertical SiO2/Ge interface. In addition, the growth against the STI-oxide side wall might be disturbed resulting in a very irregular Ge layer. Here, we describe the effect of the FIN design on the epitaxial growth process. The presence of Source/Drain contact pads has as strong influence on the Ge migration inside the narrow trench. S/D contacts act as a kind of ?sink? for mass transport. For FIN structures without large contacts, the driving force for Ge diffusion out of the trench is lower. This leads to an increase of the critical growth temperature above which filling of narrow channels is prohibited enabling an impressive improvement of the Ge crystalline quality.

O.O.4
18:00
Authors : S K Deb1, T V Chandrasekhar Rao2, D. Bhattacharya2, B. Sundaravel3, B.K. Panigrahi3
Affiliations : 1Indian Institute of Technology Bombay, Mumbai 400076, India,2Bhabha Atomic Research Centre, Mumbai 400085, India,3Indira Gandhi Centre for Atomic Research, Kalpakkam 603102, India

Resume : The discovery of ferromagnetic III-V semiconductors, like Ga1-xMnxAs with Curie temperatures (Tc) ≈ 110 K has led to intense interest in its application to ‘spintronics’. Here, the Mn2+ acts as acceptor, generating free holes in the valence band and there is a direct correlation between Tc and hole concentration. Although Raman scattering has been used for hole concentration determination in MBE grown GaMnAs, here we report the first measurement of the hole density in Mn+ implanted pulsed laser annealed GaAs using Raman scattering. Mn2+ ions at 300 keV were implanted in n-type (001)GaAs with fluence of 2x1016 ions/cm2 corresponding to a Mn concentration of 2.15% and were annealed with 25 ns pulse of an excimer laser (248 nm, 160 mJ/cm2). Raman spectra were recorded using JY HR800 confocal Micro-Raman spectrometer with 5145.5 nm Ar+ laser line. The Raman spectra did not show any separate coupled phonon-plasmon mode implying a p-type doping and instead shows a strong mode at ≈264 cm-1 (close to the TO mode) with a much weaker feature near the LO mode. Irmer et al[1] have shown tha,t with increasing hole density the coupled mode decreases in frequency and FWHM and increases in intensity till it merges with the TO mode at concentration > 10^20 /cc. Thus the observed frequency and FWHM in our Raman spectrum corresponds to a hole concentration of ≈ 10^20 /cc and µH≈ 50 cm2/Vs which agrees with Tc ≈80K from our magnetization measurement. [1] G Irmer et al, Phys Rev B56, 9524 (1977)

O.O.5
18:00
Authors : T.Matsumura, T.Furuya, T.Sato, Y.Okabe, S.Suzuki*, K.Ishibashi*, Y.Yamamoto
Affiliations : Graduate School of Science and Engineering, Hosei University; *Comet Inc.

Resume : Cerium dioxide is one of the promising materials for high-k gate film because of its high dielectric constant of 26 and compatibility with Si. It has, however, a strong tendency to poly-crystallize at relatively low temperatures. In order to suppress crystallization, we have selected the combination of CeO2 and SiO2 with different crystalline structure each other. Although Ce(OCEt2Me)4 and TEOS are known as the sources for MOCVD of CeO2 and SiO2, respectively, it is difficult to perform the simultaneous deposition of CeO2 and SiO2 by the pyrolysis because of the different decomposition temperature. We have succeeded in depositing the amorphous mixed oxide of CeO2 and SiO2 by MOCVD with intermittent TEOS introduction based on the idea that the decomposition temperature of TEOS can be lowered by the hydrolysis utilizing H2O generated during the CeO2 deposition. The XPS analyses revealed that Si existed mainly as silicate and uniformly distributed along the depth in the CeO2 film. The fact that the duration time for the TEOS introduction did not affect the amount of Si in CeO2 indicates that the amount of Si in the film is not limited by the amount of TEOS supplied but that of H2O generated in the pyrolysis of the CeO2 source. From the results of XRD, the crystallization of the CeO2 film was suppressed by mixing SiO2 even after the annealing at 500 °C, while the pure CeO2 film as deposited at 350°C represented the (111) oriented columnar poly-crystalline structure.

O.O.6
18:00
Authors : O. Ivanyuta, Yu. Pogrebnyak
Affiliations : Department Electrophysics, Faculty of Radiophysics, Taras Shevchenko National University of Kyiv

Resume : Label-free DNA sensors based on sapphire substrate were fabricated and electrochemically characterized. A low resistivity (0.01-0.02 Ω cm) ptype Al2O3 wafer (100 orientation) was electrochemically anodized in an ethanoic hydrofluoric acid (HF) solution containing ethanol to construct the sapphire substrate layer with pore diameter of about 25 nm. The intrinsic negative charge of the DNA backbone was ex ploited to adsorb 26 base pairs of probe DNA (pDNA) into the PPy film by applying positive bias forming the nPS/PPy+pDNA layer.

O.O.7
18:00
Authors : Robert Mroczyński, Magdalena Szymańska
Affiliations : Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland

Resume : Although hafnia-based dielectric materials have already replaced thermal silicon dioxide (SiO2) or oxynitride (SiOxNy) as the gate dielectric in nowadays Ultra-Large Scale Integration (ULSI) devices, there are still many important aspects have yet to be understood for hafnium oxide materials technology and processing. Thermal stability is a critical issue since several high temperature steps may be performed after gate dielectric fabrication in particular semiconductor device technology, and thus, strongly influence electro-physical properties of dielectric layers. In this work we examine changes of the properties of hafnium oxide (HfOx) and hafnium oxynitride (HfOxNy) deposited by means of radio frequency (r.f.) reactive magnetron sputtering process after elevated temperature treatment. Possible changes in structure, composition and electrical parameters were investigated by means of spectroscopic ellipsometry (SE), scanning electron microscopy (SEM) equipped with energy dispersive spectroscopy (EDS) microanalyzer, capacitance-voltage (C-V), as well as current-voltage (I-V) measurements. In the course of this work we will try to link the electrical parameters of MOS structures with changes of the chemical composition and structure of HfOx and HfOxNy gate dielectrics. All observations and findings will be carefully examined and described in order to formulate the concluding remarks on the thermal stability of hafnia-based dielectric materials.

O.O.8
18:00
Authors : V.A. Skryshevsky, Yu.S. Milovanov, I.V. Gavrilchenko, S.I. Tiagulskyi, A.V. Rusavsky, P.M. Lytvyn, V.S. Lysenko, A.N. Nazarov
Affiliations : Institute of High Technologies, Taras Shevchenko National University of Kyiv, 01601 Kyiv, Ukraine Lashkaryov Institute of Semiconductor Physics NAS of Ukraine, Kyiv, 03028 Ukraine

Resume : The impedance spectroscopy, micro-Raman scattering spectroscopy and scanning Kelvin probe force microscopy (SKPFM) techniques were applied for analysis of single graphene layer deposited by CVD technique on Cu foil with subsequent transfer on SiO2/p-Si structure. Despite that Raman spectra showed the high quality of studied layers (ratio of intensities of the D and G peaks ID/IG is better than < 0.01 and the 2D to G peaks I2D/IG ≈2) two semicircles on the Nyquist curve of Ni-graphene-Ni structure suggests the existence of inhomogeneous regions. The SKPFM technique demonstrates appearance of graphene crystallite with average size about 7-10 mkm. Exposure in ethanol and acetone vapors by different degrees affects the reactive and active resistance of graphene film. Moreover, the dynamic response behavior of impedance differs in the vapor of ethanol, acetone and phenol. It ensures that impedance spectroscopy of graphene is useful tool for detection of different gases.

O.O.9
18:00
Authors : Rahul Kumar*, Apurba Chakraborty**, Partha Mukhopadhyay***, Subhashis Das*, Dhrubes Biswas**
Affiliations : *Advanced Technology Development Centre, Indian Institute of Technology, Kharagpur, India 721302; **Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India 721 302; ***Rajendra Mishra School of Engineering Entrepreneurship, Indian Institute of Technology, Kharagpur, India 721302

Resume : A novel growth strategy for In(Al,Ga)As metamorphic graded buffers to study the effect of surface roughness on the indium incorporation has been presented in this work. Moreover, a qualitative explanation for the observed indium incorporation variation with the surface roughness has been presented. Three different pathways of metamorphic buffer have been used. On top of the graded metamorphic buffers, a thick constant composition InAlAs healing layer has been grown. MBE growth for varied growth parameters during growth has been elaborately studied. Growth parameters have been optimised such that the indium incorporation with the surface roughness can be studied. V/III ratios were different in all three cases during the graded buffer growth. But, it was kept same in all three samples during healing layer growth. Keeping all the growth parameters (V/III ratio, Individual element’s BEP, growth temperature etc.) same during the growth of healing layers ensure that the effect of surface roughness on indium incorporation rate can be studied. AFM statistical analysis and HRXRD measurements have been used to support the observation. In vacuum deposition chamber like MBE, epitaxial growth, generally, proceeds by the surface migration of incoming adatoms to the energetically more favourable sites like kinks and steps. Growth is greatly influenced by the availability of these kinks. In other words, surface morphology or growth front roughness has the potential to influence the growth process. During the growth, rougher surface provides more kink sites than the flat surfaces. These kink sites are stable nucleation centres for the adatoms. So, adatoms are fast incorporated on rougher growth front compared to adatoms diffusing on smooth growth front. Adatoms having non-unity sticking coefficients, like indium, have it because of re-evaporation of adatoms before getting incorporated. Presence of more kink sites (or rougher surface) enhance the incorporation rate of adatoms by decreasing the re-evaporation rate as the adatoms now incorporated before getting re-evaporated.

O.O.10
18:00
Authors : R. K. Savkina, A. B. Smirnov
Affiliations : V. Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine, Kiev, Ukraine

Resume : Development of multi-band detector technology is critical and remains one of the important directions for the successful development of active and passive vision. HgCdTe-based detector structure considering different semiconductor device concepts is presented. Narrow-gap HgCdTe (MCT) technologies are well developed now, and today this material is one of the basic semiconductor for photon detectors from MWIR (λ ∼ 3–5 μm) to LWIR (λ ∼ 8–14 μm) spectral range and is used in large-scale arrays with silicon CMOS readouts. Here, we describe multi-band radiation detector based on HgCdTe/Si heterostructure which exhibit sensitivity in the middle and long wavelength IR spectral range without cryogenic cooling to achieve useful performance. MCT-based heterostructure was also considered as sub-THz detector. It was observed that HgCdTe/CdTe/ZnTe/Si heterostructure exhibits photo-response under IR photoexcitation without electrical bias and amplification in MWIR region. The prototype of photovoltaic detector is also sensitive to CO2 laser radiation on the level of ~0.04 V/W at 1 mW laser beam power in focal spot. The sensitivity of MCT-based heterostructures for sub-THz radiation (the source with 140 GHz frequency was used for testing) was found after the ion beam bombardment of the sample investigated.

O.O.11
18:00
Authors : E. G. Rolseth, I. A. Fischer, K. Kostecki, R. Körner, M. Oehme, V. S. Senthil Srinivasan, J. Schulze
Affiliations : Institut für Halbleitertechnik, Universität Stuttgart, D-70569 Stuttgart, Germany

Resume : The high drive current is the major obstacle on the road towards establishing group IV based tunneling field effect transistors (TFETs) as a viable alternative to metal-oxid-semiconductor field effect transistors (MOSFETs). The on current in these devices is a band-to-band tunneling (BTBT) current and can be enhanced by increasing the BTBT probability. The bandgap and the effective carrier mass should be minimized for high barrier transparency and in this respect Ge1-xSnx is an exciting candidate. Here, we present the impact of inserting Ge1-xSnx as channel material in vertical Ge-based TFETs. The Sn concentration x in the Ge1-xSnx-channel is expected to affect device off-currents and subthreshold swing as well as device on-current. The semiconductor layer structures of the Ge1-xSnx-heterojunction TFETs are grown by means of molecular beam epitaxy (MBE) on Si (100) substrates. To suppress the strong segregation of Sn and Sb in Ge, growth of these materials are carried out at low temperatures. Graded drain doping profiles are implemented to suppress ambipolarity and ensure the correct functionality of a p-type tunneling field effect transistor. A gate-all-around fabrication process is used to fabricate vertical-TFET devices with varying device geometries. We compared three samples with different Sn concentrations in the Ge1-xSnx channel (x = 0%, 2% and 4%), and its effect on the transistors electrical characteristics is reported.

O.O.12
18:00
Authors : Krista R Khiangte1 , Jaswant S Rathore1*, Swagata Bhunia1, Sudipta Das2, Rajveer S Fandan2, A Laha2, and S Mahapatra1
Affiliations : 1Department of Physics, Indian Institute of Technology, Bombay – 400076, India; 2Department of Electrical Engineering, Indian Institute of Technology, Bombay – 400076, India

Resume : Systematic analysis of strain relaxation in Ge1-x Snx epitaxial layers, grown by molecular beam epitaxy (MBE) at low growth temperatures (TG = 100 C) on Ge (001) virtual substrates, is reported for different Sn concentrations ( x = 0 – 5%). In particular, we have estimated the dislocation density as a function of Sn concentration and layer thickness, from the analysis of full-width at half maximum (FWHM) values of omega scans in high resolution X-ray diffraction (HRXRD). The dislocation density has then been correlated to the degree of strain relaxation, determined by reciprocal space mapping (RSM) around (004) and (224) reflections, and the surface morphology, probed by atomic force microscopy (AFM). The effect of rapid thermal annealing and boron-doping of Ge1-x Snx epitaxial layers on the dislocation density, and therefore the degree of relaxation, will also be discussed. Key words: Epitaxy, MBE, HRXRD.

O.O.13
18:00
Authors : Tung Pham, Lisa Michez, Vinh Le Thanh
Affiliations : Aix-Marseille Université - CNRS CINaM-UMR, 13288 Marseille, France

Resume : The development of active spintronic devices requires an efficient spin injection into semiconductors, particularly into silicon or germanium. Germanium-based diluted ferromagnetic semiconductors (DMS) doped with Mn would be an ideal candidate owing to their natural impedance match to group-IV semiconductors. Since DMS thin films have shown their limit in magnetic properties, we proposed to investigate the growth of diluted GeMn quantum dots (QDs). QDs can be grown by self-assembly via Stranski-Krastanov mode. Thanks to the spin confinement effects and reduced spin-orbit interaction, it is expected that their magnetic properties can be greatly enhanced. Previous studies show that there are two main phenomena in the growth process, namely the formation of intermetallic clusters and the inter-diffusion between Si, Ge and Mn, which deteriorate their magnetic properties. Therefore, in our work, we focused on the growth of GeMn QDs at low temperature ranging from 350-500°C, which is expected to limit diffusion. Firstly, we study the growth of pure Ge on Si substrates to optimize growth parameters. Next, we study the growth of GeMn QDs with a small concentration of Mn (1-2%). Structural analyses (AFM, RHEED, and TEM) indicate that Mn incorporation in Ge does not affect the Stranski-Krastanov growth mode. However, Mn drastically modifies the surface diffusion phenomenon and the island morphology is very different to the one observed in pure Ge QDs.

O.O.14
18:00
Authors : Yi Ting Huang;Albert T Wu
Affiliations : Department of Chemical and Materials Engineering National Central University;Department of Chemical and Materials Engineering National Central University

Resume : Electromigration-induce back stress is generated from the gradient of vacancy across the length of Pb-free solders. The miniaturization and high integration of the electronic devices result in limited space of the solders, and the fast reaction between the solders and electrodes forms intermetallic compounds (IMCs) that usually occupy the solder volume significantly. The electromigration that occurs in the space-confined solder joints dominated by IMCs has become a new concern of the reliability. In this study, in-situ electromigration was conducted in U-groove Cu/Sn3.5Ag/Cu and Ni/Sn3.5Ag/Ni sandwich structures that were fabricated by using lithography and electroplating on Si chips. The solder gaps between the electrodes were limited to less than 15 µm to simulate the micro-solder joints. The samples were stressed by current at various current densities at 150 oC for different duration of times. The morphological evolution and the thickness of the IMCs were measured to determine the kinetic growth of IMCs. The back stress effect was directly observed in the systems. Theoretical calculations indicated that the back stress in the Sn3.5Ag was 17.4 MPa at a current density of 1 × 104 A/cm2.

O.O.15
18:00
Authors : Martin Wilhelm, Ayberk Caliskan, Peter Wellmann
Affiliations : Materials Department 6 (i-meet) FAU Erlangen Nürnberg Martnesstr. 7 91058 Erlangen, Germany

Resume : We have investigated the epitaxial growth of Si-Ge-C layers on (100) Si substrates for novel optoelectronic applications of group IV-semiconductors. The goal of the work is to tailor the electronic bandgap of 3C-SiC by the partial exchange of silicon by germanium. In particular, the reduction of the bandgap of 3C-SiC of 2.3 eV down to 1.8 eV using germanium would make SiGeC an ideal material to realize a tandem solar cell on silicon. As precursors, silane (SiH4), iso-butyl germanium and propane (C3H8) were applied. The substrate temperature during deposition varied between 1150 °C and 1300 °C. During deposition the layers tended to form SixGe1-x and elementary Ge and 3C-SiC phases, rather than building the ternary SiGeC compound. In general, a lower substrate temperature and a higher Ge/Se ratio favored the deposition of Ge. Although germanium exceeded a concentration of 12% in the Si-Ge-C layers, so far no targeted Ge-C bonds could be detected by Raman spectroscopy and X-ray diffraction. However, the observed formation of SixGe1-x and elementary Ge is believed to be of great importance for near infrared optoelectronic applications. The paper will present a detailed photoluminescence study of the Si-Ge-C layer structures and will discuss its applicability in optoelectronics.

O.O.16
18:00
Authors : Grace Flynn, Kevin M. Ryan
Affiliations : Materials and Surface Science Institute and Department of Chemical and Environmental Sciences, University of Limerick, Limerick, Ireland

Resume : Si and Ge nanowires (NWs) offer the potential for many useful applications such as in photovoltaics, energy storage and in transistor devices. Heterostructure semiconductor NWs consisting of both Si and Ge offer further advantages for their use in next generation devices. Both radial and axial heterostructure NWs of Si/Ge have been grown to date typically using chemical vapour deposition growth systems. Here, we present the synthesis of axial Si-Ge heterostructure nanowires through a wet chemical synthesis approach. Low solubility type B catalysts are chosen for the growth of these NWs in order to produce sharp transitions between the Si and Ge segments. The type B catalysts chosen for this growth are indium (In), tin (Sn) and bismuth (Bi) which have the potential for p type, intrinsic and n type doping respectively, with Si and Ge. Different ratios of Sn:In and Sn:Bi have been used in order to control and vary the potential doping effects. These NWs are characterised using high resolution transmission electron microscopy (HRTEM), dark field scanning transmission electron microscopy (DF-STEM) and energy dispersive X-ray analysis (EDX).

O.O.17
18:00
Authors : B. Salem1, V. Brouzet1,2, P. Periwal1, T. Baron1, F. Bassani1, G. Ghibaudo2
Affiliations : 1 Univ. Grenoble Alpes, LTM, F-38000 Grenoble, France CNRS, LTM, F-38000 Grenoble, France 2Univ. Grenoble Alpes3bis, IMEP-LAHC, F-38000 Grenoble, France CNRS, IMEP-LAHC, F-38000 Grenoble, France

Resume : The power dissipation associated with a high off-state current (Ioff) has become one of the major problem to the further scaling of CMOS devices. In order to decrease the Ioff and the voltage supply (VDD), it will be necessary to reduce the subthreshold slope swing (SS). In fact, the conventional MOSFET has a physical limit of SS (60mV/dec at 300K) due to the thermionic conduction mechanism. To reduce the SS, various carrier injection mechanisms have been proposed. One of the most promising low energy consumption device is the Tunnel Field-Effect Transistor (TFET) to attain steep SS, low Ioff current and high on-state current to off-state current ratio at very low VDD. The TFET consists of a gated p-i-n diode in reverse bias whose carrier transport is principally governed by band-to-band tunnelling (BTBT). In this context, we present the horizontal and vertical p-Si/i-Si/n-Si1-xGex heterostructure nanowire integration, with an in situ p(Si)-i(Si)-n(Si1-xGex) doping profile on TFET device. These nanowires were elaborated by Chemical-Vapor-Deposition using Vapor-Liquid-Solid mechanism with gold as catalyst. Doping profile along the axis of the nanowire has been evidenced using scanning capacitance microscopy. We will highlight the bandgap engineering by the Germanium concentration change on the band-to-band tunneling increase, thanks to the reduction of the band gap of the source material.

O.O.18
18:00
Authors : Doo-Hyung Kim1, Seung-Jong Oh1, Ja-Yeon Kim2, Min-Ki Kwon1,*
Affiliations : 1. Department of Photonic Engineering, Chosun University, Gwangju, Jeonnam, Korea (South) 2. Department of Photonic Engineering, Chosun University, Gwangju, Jeonnam, Korea (South)

Resume : Monolayers of semiconducting transition metal dichalcogendes (TMDs) hold significant promise in electronics and optoelectronics due to their unusual electrostatic coupling, large carrier mobility, high current carrying capacity, and strong absorption in the visible frequencies with the their chemical and mechanical robustness.[1] There are semiconducting TMDs that can be produced by combining the metals Mo with chalcogens S or Se in the form MX2. Interestingly as the number of layers is decreased their electronic properties change, with the monolayer exhibiting a direct band gap. In mineral form, MoS2 is the most abundant TMD and therefore has been extensively studied. While monolayer of MoS2 can be readily obtained by micromechanical cleavage of synthesis or natural bulk crystals, large area, high quality and continuous thin film are needed for practical devices. However, obtaining high crystal quality thin films over a large area remains a challenge. Here we report the structural and optical properties of large area electronic grade single crystal MoS2 thin films grown by chemical vapor deposition (CVD). MoS2 films grown under optimal conditions were found to be of high structural quality from high-resolution X-ray diffraction, transmission electron microscopy, and Raman measurements. The optical properties of MoS2 film will be discussed.

O.O.19
18:00
Authors : M. Grydlik, F. Hackl, H. Groiss, T. Fromherz, W. Jantsch, F. Schäffler and M. Brehm
Affiliations : Institute of Semiconductor and Solid State Physics, Johannes Kepler University Linz, Altenbergerstrasse 69, 4040 Linz, Austria

Resume : Epitaxially grown Ge quantum dots (QDs) in a fully coherent Si matrix can exhibit extraordinary optical properties if they are partly amorphised by low-energy Ge-ion bombardment (GIB). The GIB-QDs exhibit a quasi-direct-band gap, type-I band alignment of excited states and a high activation energy for thermal quenching of about 350 meV due to efficient electron localization at dangling bonds. As a consequence of the high activation energy, the GIB-QDs show, in contrast to conventional SiGe nanostructures, almost no thermal quenching of the photoluminescence up to room-temperature. In this work we evaluate the influence of the QD shape (domes, pyramids, hut-cluster and shallow surface undulations), chemical composition (from 40% to 100% of Ge) within the QDs and energy of the impinging Ge ions (from 0 keV to 3 keV) on the optical properties of the GIB-QDs. We embedded the GIB-QDs of hut-cluster-shape into photonic resonator structures such as photonic crystal cavities and microdisk resonators. The resonators containing GIB-QDs exhibit threshold-behavior and super-linear increase of the integrated PL-intensity with increasing excitation power. Additionally, a clearly defined mode pattern in combination with linewidth narrowing above threshold indicates light amplification by stimulated emission in a group-IV nanosystem. This system is compatible with standard integrated Si technology as the GIB-QDs are simply embedded in a fully crystalline Si matrix.

O.O.20
18:00
Authors : H. Ferhati1, F. Djeffal1,2,* and D. Arar1
Affiliations : 1) LEA, Department of Electronics, University of Batna, Batna 05000, Algeria. 2) LEPCM, University of Batna, Batna 05000, Algeria. *) E-mail: faycal.djeffal@univ-batna.dz, faycaldzdz@hotmail.com Tel/Fax: 0021333805494

Resume : The CMOS technology has emerged over the last years as a promising class of techniques for optoelectronic applications, due to the superior optical and electrical properties offered by this technology for both in digital as well as in analog applications. Optically controlled field effect transistors (OC-FETs) are promising devices to overcome the undesired high power dissipation and limited bandwidth effects. However, the use of uniformly doped gate presents the well-known problem of the low commutation speed and high subthreshold swing effect, which degrade the electrical performance of the device. Therefore, in order to improve the OC-FETs performance under optical excitation, new design aspects are required. Based on numerical investigation of OC-FETs, in the present paper a Gate-Engineering-based-approach to improve the submicron OC-FET electrical and optical performance is presented. In this context, I-V, voltage gain and subthreshold characteristics of the proposed design are investigated and compared with conventional OC-FET characteristics. The proposed design provides a good solution to improve the drain current and the commutation behavior for high-performance communication applications.

O.O.21
18:00
Authors : K. Kacha1, F. Djeffal1,2,*and H. Ferhati1
Affiliations : 1) LEA, Department of Electronics, University of Batna, Batna 05000, Algeria. 2) LEPCM, University of Batna, Batna 05000, Algeria. *) E-mail: faycal.djeffal@univ-batna.dz, faycaldzdz@hotmail.com Tel/Fax: 0021333805494

Resume : III-V/Si-based tandem solar cells have emerged over the last years as promising candidates for space and terrestrial application due to the high efficiency, light weight and low cost potential offered by this technology. However, the problem of the high density of dislocations at the interface III-V/Si should be investigated. Therefore, new experimental, theoretical and numerical studies which capture the accurate III-V/Si-based solar cells behavior should be developed in order to build a complete and accurate III-V/Si-based solar cell model for photovoltaic applications. In this paper, we aim at highlighting the immunity behavior of the GaAs/Si heterostructure against the defects degradation. The impact of the interfacial defects on the solar cell performance has been carried out by extensive simulation using Atlas 2-D simulator and ANFIS-based computation in order to predict the device behavior under critical conditions. The developed approach can be implemented into circuit simulators such as SPICE and PC1D in order to optimize the photovoltaic circuit performances.

O.O.22
18:00
Authors : B. Baert, S. Gupta, F. Gencarelli, R. Loo, E. Simoen, N. D. Nguyen
Affiliations : Department of Physics, University of Liege, Belgium; MTM Department, KU Leuven, Belgium; MTM Department, KU Leuven, Belgium; imec, Belgium; imec, Belgium; Department of Physics, University of Liege, Belgium

Resume : Germanium-tin (GeSn) semiconductor alloys are promising materials for the fabrication of silicon-compatible optoelectronic devices. Indeed, the feasibility of a direct bandgap compound for Sn concentration in the range of 10% opens the way to the development of optical applications in the infrared region. This material class is also envisioned as a potent carrier mobility booster through strain engineering in field-effect transistors (FETs), either as a channel material or as a stressor material. In view of the development of GeSn metal-oxide-semiconductor FETs, we report the electrical characteristization of pGeSn/nGe mesa junction diodes. These were made of a 200 nm thick boron-doped GeSn layer grown by chemical vapor deposition on top of a 450 µm Ge substrate. We observed large transient currents as well as huge hystereses when reverse-biasing the diodes. Based on experiments, which consisted in appropriate dips of the diodes into H2O2, we attribute these effects to the non-passivation of the sidewalls of the mesa structures, where coverage by the native GeSnOx is responsible for the particular electrical response that we reported. Temperature-dependent measurements as well as sequences of forward and reverse biasing and illumination of the diodes allowed us to investigate the properties of theses transients currents, and to propose a model for the parallel sidewall conduction by means of an equivalent electrical circuit.

O.O.23
Start atSubject View AllNum.
 
Integration I : Giovanni Capellini
09:00
Authors : C. Merckling1;a, S. Jiang1;2, Z. Liu1;2, N. Waldron1, N. Collaert1, M. Heyns1;2, Z. Wang3, B. Tian3, M. Pantouvaki1, J. Van Campenhout1, D. Van Thourhout1;3, W. Vandervorst1;2, A. Thean1
Affiliations : (1) imec, Kapeldreef 75, 3001, Leuven, Belgium; (2) Katholieke Universiteit Leuven, Celestijnenlaan 200D , 3001, Leuven, Belgium; (3) Ghent University / INTEC, Sint-Pietersnieuwstraat 41, 9000, Gent, Belgium

Resume : Monolithic integration of III-V semiconductors epitaxially grown on Si substrate have been attracting much attention as building blocks for next-generation electronics and photonics due to their potential intrinsic properties. We report here on the growth of InP and related compounds on STI patterned Si wafers by Selective Area Metal-Organic Vapor Phase Epitaxy. Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds. We investigated the fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. As a conclusion, this study of III-V selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on (001) oriented Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is original and obviously confirm the potential of this heterogeneous integration option for high mobility logic devices, and photonic applications on a common Si platform.

O.4.1.1
09:30
Authors : L. Czornomaz(1), E. Uccelli(1), M. Sousa(1), V. Deshpande(1), V. Djara(1), D. Caimi(1), M. D. Rossell(2), R. Erni(2) and J. Fompeyrine(1)
Affiliations : (1)IBM Research GmbH Zürich Laboratory, Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland (2)EMPA, Electron Microscopy Center, Uberlandstrasse 129, 8600 Dübendorf, Switzerland

Resume : Heterogeneous integration of compound semiconductors on silicon is the Holy Grail for many technologies that are critical for the society today. Low power CMOS digital circuits, high performance wireless analog systems, low cost integrated photonic circuits – to name a few – would greatly benefit from such an innovation. Moreover, most of these applications would benefit from having the compound semiconductor layer on top of an insulator. Many approaches have been considered, taking advantage of the defect reduction in thick buffers using wafer bonding, or of defect filtering in nanoepitaxial concepts such as epitaxial lateral overgrowth or aspect ratio trapping. We report here on the demonstration of the integration of high-quality InGaAs or InP on insulator on Si substrates, using a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based on selective epitaxy, only requires the use of standard large-area silicon substrates and typical CMOS processes. Its key feature is to rely on a geometrical filtering of defects, using changes in the growth direction rather than in the dimensions of the grown crystal. It enables the fabrication of “on-insulator” structures starting from both bulk and SOI Si wafers. The InGaAs and InP epitaxial structures are characterized by a very low defectivity. Such substrates can fulfill the requirements of advanced CMOS nodes, as exemplified by the demonstration of short channel, gate-first, self-aligned FinFETs with excellent electrical characteristics. The device metrics are comparable to state-of-the-art InGaAs MOSFETs on Si, highlighting the potential of our approach.

O.4.1.2
09:45
Authors : F. Bassani1, R. Alcotte1, V. Gorbenko1,2, M. Billaud1,2, R. Cipro1, M. Martin1, J. Moeyaert1, S. David1, J.P. Barnes2, N. Rochas2,Y. Bogumilowicz2, H. Boutry2, N. Chauvin3, J.B. Pin4, X. Bao4, E. Sanchez4, and T. Baron1
Affiliations : 1 Univ. Grenoble Alpes, LTM, F-38000 Grenoble, France CNRS, LTM, F-38000 Grenoble, France 2 Univ. Grenoble Alpes, F-38000 Grenoble, France CEA, LETI, MINATEC Campus, F-38054 Grenoble, France 33 Institut des Nanotechnologies de Lyon (INL)-UMR5270-CNRS, INSA-Lyon, Universite de Lyon, 7 Avenue Jean Capelle, 69621 Villeurbanne, France 4 Applied Materials, 3050 Bowers Avenue, Santa Clara, California 95054, USA

Resume : The integration of III-V materials having high carrier mobility and direct band gap on silicon substrates is an important issue for future microelectronic and optoelectronic applications, and has received renewed interest in recent years. However, the epitaxy of III-V materials on Si presents many difficulties, mainly because of the large difference in lattice parameter (>4%) and the polar/non-polar character of layer/substrate interface, thereby generating numerous structural defects such as dislocations and antiphase domain boundaries (APBs) in the epitaxial layers. We will focus on our latest achievements in the growth and properties of III-As heterostructures by metal organic chemical vapor deposition on (100)-oriented Si substrates, and also on patterned substrates. The optimization of growth parameters has enabled us to obtain thin GaAs epitaxial layers on blanket Si(100) substrates free of APBs. Room temperature µPhotoluminescence and low temperature cathodoluminescence results obtained on these layers will be presented, as well as their electronic properties obtained by Hall effect measurements. Also, the selective area growth in oxide trenches provides layers of high structural and optical quality near the top of cavities, by blocking most of dislocations in the oxide walls. The physicochemical characterization of these 3D structures obtained by ToF-SIMS, in correlation with their optical properties, will be presented. The results open the path for the integration of III-As based materials on a CMOS Si platform.

O.4.1.3
10:00
Authors : Weiming Guo, Yves Mols, Robert Langer, Kathy Barla, Matty Caymax, Bernardette Kunert, Lucien Date, Xinyu Bao, David Carlson, Errol Sanchez
Affiliations : Weiming Guo; Yves Mols; Robert Langer; Kathy Barla; Matty Caymax; Bernardette Kunert; IMEC, Kapeldreef 75, 3001 Leuven, Belgium Lucien Date; Xinyu Bao; David Carlson; Errol Sanchez; Applied Materials, 3050 Bowers Avenue, Santa Clara, California 95054, USA

Resume : The monolithic integration of III-V materials with high electronic mobility and direct bandgap on silicon substrate is expected to further boost the electronic and photonic device performance. Hetero-epitaxial growth of high quality GaAs and GaAs based materials such as AlGaAs, InGaAs, and InGaP on 300mm silicon is of great importance for this goal. The main obstacle to high quality epitaxial GaAs layer atop Si is the formation of threading dislocation due to 4% lattice mismatch and of Anti-Phase Domains (APD) caused by a different polarity. The Selective Area Growth (SAG) technique affords to tackle these difficulties while remaining cost?effective. The dislocations are confined at bottom part via dielectric dislocation trapping, leaving a high quality upper layer whereas V-shape (111) Si facets at the bottom of active area prevent APD during the nucleation step. We will present a systematic study on SAG MOVPE growth of GaAs and InGaAs on 300mm silicon with Shallow Trenches Isolation (STI) patterning. Growth characteristics differing from blanket deposition, such as strain relaxation, growth rate and facet formation as a function of the growth parameters, will be discussed. The obtained III-V layer is of good crystal quality and ends up with a (001) top surface for well-chosen growth conditions. This serves as a good platform for integrating other active III-V layers. As an example, the potential application of InGaAs in electronic and photonic devices will be presented.

O.4.1.4
10:15
Authors : Charles RENARD1, T. Moli?re1,2, N. Cherkashin3, A. Jaffr?2, L. Vincent1, J. Alvarez2, D. Mencaraglia2, D. Bouchier1
Affiliations : 1 IEF, CNRS-UMR 8622, Bat 220, Univ Paris-Sud, 91405 Orsay, France 2 GeePs, UMR 8507 CNRS, Sup?lec, Universit?s Paris VI et XI, 11 rue Joliot Curie, 91192 Gif-sur-Yvette 3 CEMES-CNRS, Universit? de Toulouse, 29 rue J. Marvig, Toulouse, 31055, France

Resume : The interest in the integration of GaAs on Si is becoming stronger each year and is guided by applications in highly active areas such as silicon-based microelectronics technologies or photovoltaic. Significant improvements have been reported for many years, thanks to selective area epitaxy of GaAs on Si substrates patterned with dielectric films. However, these layers are inappropriate for applications involving electronic transport between GaAs and Si at a large scale. To overcome these problems we have developed a technique based on the epitaxial lateral overgrowth (ELO) of micrometer scale GaAs crystals on a 0.6 nm thick SiO2 layer from nanoscale Si seeds. The nucleation from small width openings enables to avoid the emission of misfit dislocations and the formation of antiphase domains. Besides, as the thickness of the oxide interfacial layer is sufficiently thin, a tunneling current may occur and lead to interfacial conductivity between GaAs and Si. Transmission electron microscopy analyses indicate that GaAs islands are defect free and perfectly integrated with the Si substrate. Additional measurements by confocal Raman microscopy and ?-PL, confirm the good quality of epitaxial GaAs layer. Finally, conductive AFM and EBIC I-V measurements were also performed and show that the heterojunction between GaAs and Si through the thin SiO2 interfacial layer is highly conductive. These different results will be presented and discussed during the communication.

O.4.1.5
10:30 Coffee break    
11:00
Authors : I. Prieto1, R. Kozak2, O. Skibitzki3, G. Capellini3, T. Schroeder3, M. D. Rossell2, R. Erni2, E. Gini4, K. Kunze5, R. Kaufmann2, A. Neels2, A. Dommann2, G. L. Bona2, and H. von Känel1
Affiliations : 1 Laboratory for Solid State Physics, ETH Zürich, Otto-Stern-Weg 1, CH-8093 Zürich, Switzerland; 2 Empa-Swiss Federal Laboratories for Materials Science & Technology, CH-8600 Dübendorf, Switzerland; 3 IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany; 4 FIRST Center for Micro- and Nanoscience, ETH Zürich, 8093 Zürich, Switzerland; 5 Electron Microscopy Center ETH Zürich, Wolfgang‐Pauli‐Strasse 16, CH-8093 Zürich, Switzerland

Resume : Si and GaAs are prominent materials to build microelectronics and optoelectronics devices, respectively. Their integration in epitaxial heterostructures is expected to provide superior device performance in electronic and optoelectronic devices [1]. The epitaxial growth of GaAs directly on Si is, however, a non-trivial endeavour due to their different structural and thermal characteristics, leading to misfit dislocations, anti-phase domains and other defects. Our approach aims at defect-free nucleation of GaAs on Si(001) by making use of Si nano-templates. Those substrates consist of arrays of Si tips [2] or pillars [3] embedded in a SiO2 matrix. They exhibit a circular top (001) opening with a diameter of 18-80 nm. GaAs nano crystals were selectively grown on the Si nano-patterns by MOVPE. Different morphologies resulted for the GaAs nano crystals depending on both the initial height and morphology of the tips and the deposited material. Single GaAs(001) crystal orientation was achieved for some nuclei, as demonstrated by EBSD. As an alternative approach, GaAs crystals were nucleated over tips with an engineered top surface. {111} nano facets were obtained by EDP based selective etching. To evaluate the crystal quality, μ-PL and Raman spectroscopy, as well as HR-SEM, HR-TEM and HR-XRD analysis are in progress. [1] Y. B. Bolkhovityanov et al., Physics-Uspekhi 51 (2008). [2] W. Mehr et al., Microelectron. Eng. 30 (1996). [3] G. Kozlowski et al., Appl. Phys. Lett. 99 (2011).

O.4.2.1
11:15
Authors : Y. Bogumilowicz1, N. Rochat1, C. Licitra1, F. Bassani2, V. Gorbenko1,2, R. Cipro2, M. Martin2, J. Moeyaert2, J.M. Hartmann1, J.P. Barnes1, J.B. Pin3, X. Bao3, E. Sanchez3, and T. Baron2
Affiliations : 1 Univ. Grenoble Alpes, F-38000 Grenoble France, CEA, LETI, MINATEC Campus, F-38054 Grenoble, France; 2 Univ. Grenoble Alpes, F-38000 Grenoble France, CNRS-LTM, F-38054 Grenoble, France; 3 Applied Materials, Santa Clara, California, United States

Resume : The integration of III-Vs on a silicon platform would bring together the better of two worlds: the high integration density, high volume, mainstream silicon technology with the high frequency, direct bandgap and wide flavor of III-V alloys, greatly extending the functionalities of tomorrow’s microchips. To that end, we have first of all grown on standard 300 mm Si(001) substrates rather thick (~ 1 µm) Ge layers in a group-IV RPCVD equipment (in order to accommodate the 4 % lattice mismatch between Si and GaAs). This will save costly III-V organometallic precursors and yield higher crystalline quality layers. We have then grown in an Applied Materials MOCVD tool ~ 300 nm thick GaAs layers on top of those Ge buffers. We have explored the impact of temperature, pressure, growth rate and V/III gas phase ratio on the nucleation of GaAs on Ge. With optimized growth conditions, we have obtained GaAs layers that were uniform (<2% standard deviation over the whole 300 mm wafer), smooth (<1 nm RMS AFM 5x5 µm2 roughness), nearly Anti-Phase Boundaries - free and with a threading dislocation density of a few 107 cm-2 only. Photo- and cathodo-luminescence measurements have been performed on those GaAs layers, together with high resolution X-ray diffraction. The GaAs layers were slightly tensile strained, n-type doped (diffusion of Ge atoms) and of high optical quality. A GaAs on Ge on Si approach thus seems suitable for the integration of As- and P-based III-Vs on large diameter substrates

O.4.2.2
 
Integration II : Charles Cornet
11:30
Authors : D. Massy, F. Mazen, D. Landru, N. Ben Mohamed, S. Tardif, F. Madeira, A. Reinhardt, A. Barthelemy, O. Kononchuk, and F. Rieutord
Affiliations : CEA-INAC - Grenoble, France CEA-LETI - Grenoble, France SOITEC - Bernin, France

Resume : The Smart Cut™ technology is a generic way of transferring very thin layers of crystalline material onto a mechanical substrate. It is currently the industrial standard for Silicon-On-Insulator (SOI) manufacturing. If the implantation and wafer bonding steps involved in this technology have been broadly studied, the fracture dynamics of the layer transfer has not drawn much attention yet. However, the ever decreasing thickness of SOI substrates requested by the microelectronics industry calls for a multiscale understanding and control of the fracture step. A good illustration of the fracture footprint is the appearance on post-split SOI wafers of a macroscopic periodic pattern made of roughness variations on large periods. We report that this pattern comes from the interaction of the fracture front with self-generated acoustics waves that can deviate the crack tip after reflection at the wafer edges. Experimentally, symmetric and antisymmetric Lamb waves are found to propagate at high velocities ahead the fracture front. The antisymmetric mode appears to be periodic and its frequency evolution with fracture velocity is carefully studied. The frequency selection is explained as the result of the stationary phase principle introduced by Lord Kelvin to describe the formation of boat wakes. Finally, numerical simulations based on acoustic phase contributions are performed to recover the typical pattern shape, with results consistent with experimental data.

O.4.2.3
11:45
Authors : V. Dragoi, N. Razek, C. Flötgen, M. Wimplinger, M. Eibelhuber, T. Uhrmann
Affiliations : EVGroup, St. Florian am Inn, Austria

Resume : Emerging “More than Moore” and photonic application benefit tremendously by close integration of compound semiconductor materials. Heterogeneous integration allows combining one to combine the benefits of mature Si silicon technology and the superior properties of compound semiconductor materials. This leads to significant performance increases or novel capabilities at comparatively low costs. This demand for integration is not limited to CMOS wafers and can be extended to economically preferred substrates in general. Epitaxial growth of compound semiconductors on e.g. silicon substrates has made substantial progress; however, the high defect rates at the growth interface, the slow growth rate of the material from the epitaxial process, and the cost of the epitaxial equipment remain very challenging. Thus wafer bonding is identified as one of the key processes to meet the needs for heterogeneous integration of compound semiconductors. This paper will focus on direct bonding methods, process requirements for combining different materials and resulting bond strength and interface properties. Besides a short overview about the status quo of plasma activated direct bonding it will explore on new technologies as oxide free wafer bonding with electrically conductive interfaces. This process is enabled by removal of the undesired oxide layer with a dry process utilizing energized particles and bonding in a high vacuum chamber.

O.4.2.4
12:00
Authors : Joydeep Ghosh, Dmitry Osintsev, Viktor Sverdlov, and Siegfried Selberherr
Affiliations : Institute for Microelectronics, TU Wien

Resume : Silicon, the main element of microelectronics, appears to be the perfect material for spin-driven applications. Purely electrical spin injection in silicon from a ferromagnetic contact at room temperature has been successfully demonstrated. The spin lifetime in bulk silicon is limited by phonon-assisted electron scattering between non-equivalent valleys. In bulk silicon biaxially stressed in the (001) plane the valley degeneracy is partly lifted which results in a several times spin lifetime enhancement depending on the spin injection orientation. However, experimentally observed large spin relaxation in confined (001) silicon structures, where the valley degeneracy is lifted in a similar fashion, demands a deeper understanding of the fundamental spin relaxation mechanism in UTB films. Spin relaxation mechanisms due to surface roughness and acoustic phonons determine the spin lifetime in (001) films. The spin lifetime is limited by electron transitions between the equivalent unprimed subbands. Shear strain due to tensile stress in [110] direction lifts the degeneracy between the two equivalent unprimed subbands in a controllable way. This reduces the main component of the spin relaxation due to inter-subband scattering. We also demonstrate an increase of the spin lifetime, when the spin injection direction is gradually drawn from perpendicular to the film towards in-plane. This work is supported by the European Research Council with grant #247056 MOSILSPIN.

O.4.2.5
12:15
Authors : B. Vianne(a,b), S. Escoubas(b), M.-I. Richard(c), A. Farcy(a), T. Schülli(c), O. Thomas(b)
Affiliations : (a)STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France. (b)Aix-Marseille Université, CNRS, IM2NP UMR 7334, Campus de Saint-Jérôme, Avenue Escadrille Normandie Niemen, Case 142, 13397 Marseille Cedex, France. (c)ID01-ESRF, 71 avenue des Martyrs, 38000 Grenoble, France.

Resume : Thermal strain is known to occur in silicon around Through Silicon Vias (TSVs), due to the coefficient of thermal expansion mismatch between Cu and Si. In parallel, new trends in 3D Integration imply the fabrication of Si photonic devices like waveguides in Silicon-On-Insulator (SOI) substrates containing TSVs. While TSV impact on devices performances has been reported, quantitative analysis of strain in active area around TSVs is still missing. In this letter TSV-induced strain in SOI layer is investigated using advanced scanning X-ray nano-diffraction. This technique consists in a quick mapping of strain of crystallographic planes with a sensitivity of 10-5 in a large area. The crystallographic offset between the 300 nm SOI top layer and the bulk substrate under the 700 nm buried oxide (around 0.3 °) allows for decorrelating strain in the two Si layers. Two-dimensional continuous mappings of 50x50 µm with 500 nm spatial intervals at two different reciprocal space positions (Si004 and Si224) were performed around a single TSV at room temperature and during in situ annealing. At each real space position, scattering images are recorded with a fast 2D detector for every point along a rocking curve and strain maps are finally obtained by fitting 3D Bragg peaks in reciprocal space. The experimental results are in good agreement with finite element analysis and reveal that strain values are mainly localized in 300 nm SOI layer, compared to bulk Si.

O.4.2.6
12:30 Lunch break    
 
Integration III : Clement Merckling
14:00
Authors : C. Cornet1, O. Skibitzki2, M. Bahri3, Y. Ping Wang1, P. Guillemé1, M. Da Silva1, R. Tremblay1, P. Râle4, S. Charbonnier5, P. Turban5, L. Largeau3, G. Patriarche3, L. Lombez4, Y. Dumeige1, Y. Yamamoto2, P. Zaumseil2, M. A. Schubert2, T. Rohel1, C. Levallois1, A. Letoublon1, J.-F. Guillemoles4, T. Schroeder2,6, Y. Léger1 and O. Durand1
Affiliations : 1 UMR FOTON, CNRS, INSA-Rennes, Université de Rennes 1, Enssat, F-35708 Rennes, France; 2 IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany; 3Laboratoire de Photonique et Nanostructures, CNRS UPR 20, Route de Nozay, 91460 Marcoussis, France; 4 Institut de Recherche et Développement sur l'Energie Photovoltaïque (IRDEP), UMR 7174 - CNRS-EDF-ENSCP, EDF R&D, 6 quai Watier, 78401 Chatou Cedex, France; 5 Département Matériaux Nanosciences , Institut de Physique de Rennes UMR UR1-CNRS 6251, Université de Rennes 1, F-35042 Rennes Cedex, France; 6 Brandenburgische Technische Universität Cottbus-Senftenberg, Konrad-Zuse Str. 1, 03046 Cottbus

Resume : In this communication, we report on the development of an (In)GaP platform monolithically integrated on silicon for photonics and energy. The realization of a low defect density GaP/Si(001) platform is first presented with growth developments and associated structural characterizations (synchrotron and lab XRD setup, STM and TEM): the main result being the early annihilation of antiphase domains around 10nm of the GaP/Si interface.[1] As an illustration of the GaP/Si platform potential, three optical devices integrated on silicon will be presented: (i) a GaAsPN/GaP/Si photovoltaic solar cell for the development of a tandem architecture on silicon,[2] (ii) an electrically-driven GaAsPN/GaP/Si light emitting diode for further laser developments and its integration with CMOS and (iii) a GaP/Si microdisk which could be potentially used for non-linear conversion and lasing. Finally, the advantages provided by the addition of indium in GaP will be discussed in terms of bandgap engineering, and carrier mobility.[3] Preliminary results toward the development of an InGaP/SiGe/Si platform will be presented. [1] Y. Wang et al., J. Appl. Cryst., (in press 2015). [2] S. Ilahi et al., Sol. Energy Mater. Sol. Cells (in press 2015). [3] O. Skibitzki et al., J. Appl. Phys. 115, 103501 (2014).

O.4.3.1
14:30
Authors : Oliver Skibitzki1, Yuji Yamamoto1, Peter Zaumseil1, Markus Andreas Schubert1, Rozenn Bernard2, Yanping Wang2, Tony Rohel2, Antoine Letoublon2, Karine Tavernier2, Olivier Durand2, Charles Cornet2, and Thomas Schroeder1-3,
Affiliations : 1 IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany; 2 UMR FOTON, CNRS, INSA-Rennes, F-35708 Rennes, France; 3 Brandenburgische Technische Universität Cottbus-Senftenberg, Konrad-Zuse Str. 1, 03046 Cottbus;

Resume : Large scale monolithic integration of InGaP on low-cost and high-thermal-conductivity Si(001) is interesting as platform for future technologies (e.g. optical devices, solar cells and wide-bandgap transistors)[1-5]. In addition to known fundamental issues of III-V-integration on Si, the InGaP/Si lattice mismatch (increasing with In content) is significant. It results in a low critical thickness and beyond it in generation of misfit dislocations, especially at higher temperatures [3]. One solution for misfit reduction is N-incorporation in InGaP. This, however may affect the electronic band structure and is limited by N-solubility and thermal stability issues [3,4]. In our approach, the lattice constant of Si is increased by Ge (perfectly miscible) insertion, in order to create a relaxed SiGe buffer alloy, lattice-matched to the chosen InGaP at growth temperature [3]. A full material growth and defect study of 20 - 40 nm In1-xGaxP [x = 0 – 0.15]/400 nm relaxed Si0.872Ge0.128-bulk buffer/Si(001) heterostructures will be presented, including its heteroepitaxial growth of SiGe by RPCVD and In1-xGaxP by MBE as well as its investigation by AFM, XRD, TEM and STEM-EDX measurement techniques. [1] T. Quinci et al., J. Cryst. Growth 380, 157 (2013). [2] O. Skibitzki et al., J. Appl. Phys. 111, 073515 (2012). [3] O. Skibitzki et al., J. Appl. Phys. 115, 103501 (2014). [4] J. Kuyyalil et al., J. Cryst. Growth 377, 17 (2013). [5] K. Volz et al., J. Cryst. Growth 315, 37 (2011).

O.4.3.2
14:45
Authors : R. Comyn1- 2, Y. Cordier1, V. Aimez2, H. Maher2
Affiliations : 1. CRHEA-CNRS, Rue Bernard Gregory, Valbonne, 06560, France. 2. Laboratoire Nanotechnologies Nanosystèmes (LN2)- CNRS UMI-3463, Université de Sherbrooke, 3000 Boulevard Université, Sherbrooke, J1K OA5, Québec, Canada.

Resume : In this work, we investigate the growth of GaN High Electron Mobility Transistors (HEMTs) for monolithic integration with Silicon CMOS circuits. The present CMOS-first approach relies on the ammonia-MBE growth of AlGaN/GaN heterostructures on masked Silicon substrates. The presence of CMOS devices on the wafer is a challenge that has been addressed by reducing the maximum growth temperature of (Al,Ga)N buffer materials from 920°C to 830°C without any degradation of the GaN crystal quality as assessed by X-ray diffraction. This is a noticeable difference compared to the MOCVD technique with materials grown at temperatures superior to 1000°C. In addition, we develop dielectric stacks able to withstand the large stress arising from the growth process and to eliminate the delamination issue due to the large difference in thermal expansion coefficient between GaN and Silicon. Hall effect measurements confirm the quality of the epilayers. Capacitance-voltage measurements show that the HEMT epitaxial structures provide a capacitance plateau with a sharp pinch-off behavior attesting the absence of significant contaminations. More, transistors show output characteristics in agreement with the previously assessed transport properties and reduced electrical leakage in spite of the presence of a dielectric mask on the Silicon substrate. This is a progress compared to previous local area ammonia-MBE works where buffer contamination had to be compensated with impurities like Carbon.

O.4.3.3
15:00
Authors : Jean-Marc Girard, PhD.
Affiliations : Air Liquide Advanced Materials

Resume : In the last 20 years, numerous new CVD and ALD materials have been adopted by the semiconductor industry to cope with the challenges posed directly or indirectly by the continued scaling of IC chips. New precursors are now being used for depositing a vast variety of films ranging from SiOC:H low-k dielectric films, to ultrathin high-k materials for gate oxides, metal barrier/adhesion layers for metallization, or advanced channel materials. More recently, the massive adoption of Atomic Layer Deposition ((PE)-ALD) has stressed the importance of precursor (and co-reactant) chemistry, as such processes have fewer adjustment knobs than classical CVD, and rely mostly on surface reaction to yield films with the desired properties. The tuning of precursor reactivity by screening ligand(s) has led to an enormous academic and industrial research effort, at the crossroad of fundamental chemistry and semiconductor process development. While mainly driven by the resulting film properties (electrical, mechanical, optical), the selection of a precursor is also conditioned by permissible process conditions (temperature, throughput, compatibility with underlying layers and subsequent process steps), and by more prosaic yet critical industrial aspects such as cost, safety & environmental concerns, ease of facilitization in a SC Fab, as well as the possibility to deliver such material in stable and perfectly reproducible conditions. Through a few real life examples, the presentation will explain the drivers for such new molecule designs, and the tradeoffs that are sometimes necessary to make them industrially viable as we venture into the 1X nodes.

O.4.3.4
15:30 Coffee break    
 
Integration IV : Jean-Marc Girard
16:00
Authors : Francesco Montalenti(1), Roberto Bergamaschini(1), Marco Salvalaglio(1), Rainer Backofen (2), Fabrizio Rovaris(1), Marco Albani(1), Anna Marzegalli(1), Axel Voigt (2), and Leo Miglio(1)
Affiliations : (1) (1) L-N ESS and Dipartimento di Scienza dei Materiali, Via R. Cozzi 55, 20126 Milano (Italy); (2) Institut fur Wissenschaftliches Rechnen, Technische Universitat Dresden, 01062 Dresden, Germany

Resume : Integration of different materials, such as GaAs or Ge, on Si via heteroepitaxy is nowadays a key step involved in the fabrication of a multitude of devices, some already in the market. However, full control over the different, sometimes competing phenomena taking place during deposition [1] has yet to be reached. Simulations can be precious in limiting the growth-parameter space to be sampled in actual experiments when searching for the desired system quality and morphology. In this work we present a continuum approach able to tackle heteroepitaxy while matching typical experimental sizes and time scales. A convenient and general description of surface-energy anisotropy is introduced [2] and several illustrative applications to semiconductors are described, exploiting both Phase-Field and sharp-interface approaches. Successful comparison with experiments is demonstrated for qualitatively different systems. We also discuss how to simultaneously tackle elastic and plastic relaxation. In particular, we show how the stress field associated with an assigned distribution of misfit dislocations can be computed on the fly, its contribution to the surface chemical potential deeply influencing the growth mode and/or the morphology of the growing front. [1] F. Montalenti, D. Scopece, and Leo Miglio, Comptes Rendus Physique 14 (7), 542-552 (2013). [2] M. Salvalaglio , R. Backofen , R. Bergamaschini , F. Montalenti , and Axel Voigt, Cryst. Growth Des. (2015); (DOI:10.1021/acs.cgd.5b00165)

O.4.4.1
16:30
Authors : Roberto Bergamaschini (1), Marco Salvalaglio (1), Fabio Isa (2), Andrea Scaccabarozzi (1), Giovanni Isella (3), Rainer Backofen (4), Axel Voigt (4), Anna Marzegalli (1), Giovanni Capellini (5), Oliver Skibitzki (5), Yuji Yamamoto (5), Thomas Schroeder (5), Hans von Känel (2), Francesco Montalenti (1), Leo Miglio (1)
Affiliations : (1) L-NESS and Department of Materials Science, Università di Milano-Bicocca, via R. Cozzi 55, I-20125, Milano, Italy; (2) Laboratory for Solid State Physics, ETH Zürich, Otto-Stern-Weg 1, CH-8093, Zürich, Switzerland; (3) L-NESS and Department of Physics, Politecnico di Milano, Via F. Anzani 42, I-22100, Como, Italy; (4) Institut für Wissenschaftliches Rechnen, Technische Universität Dresden, Zellescher Weg 12-14, D-01069, Dresden, Germany; (5) IHP, Im Technologiepark 25, D-15236, Frankfurt (Oder), Germany

Resume : The move from dimensional to functional scaling in microelectronics has recently revamped the interest towards integration of high-quality Ge on Si [1]. However, due to the 4% lattice misfit, this is quite a technological challenge. In ref. [2] we showed the possibility to grow vertically-aligned micrometric Ge crystals, separated by nanometric gaps, on top of Si pillar patterned substrates, without dislocations at the top region. Herein we show by simulation-driven experiments, how these structures can evolve into a suspended Ge film by simply exploiting their temperature-driven coalescence. By closely comparing experimental data and simulation results based on a phase-field model of surface diffusion [3], we demonstrate that the massive morphological evolution is essentially driven by the lowering of surface-curvature gradients. Scanning Tunneling Electron Microscopy (STEM) and High Resolution - Transmission Electron Microscopy (HR-TEM) measurements indicate that the resulting film has very high crystal quality. In particular, dislocations are not observed to nucleate when the crystals start to coalesce, as confirmed by etch-pit analysis. Our approach thus provides a viable path for the integration on Si of Ge layers with very low defect density. [1] R. Pillarisetty, Nature 479, 324 (2011) [2] C.V. Falub et al., Science 335, 1330 (2012) [3] M. Salvalaglio, R. Backofen, R. Bergamaschini, F. Montalenti, A. Voigt, Cryst. Growth Des, in press (doi: 10.1021/acs.cgd.5b00165

O.4.4.2
16:45
Authors : Emile Maras, Oleg Trushin, Tapio Ala-Nissil?, Hannes J?nsson
Affiliations : Department of Applied Physics and COMP Center of Excellence, Aalto University School of Science, FIN-00076 Aalto, Espoo, Finland; Institute of Physics and Technology, Yaroslavl Branch, Academy of Sciences of Russia, Yaroslavl 150007, Russia; Department of Applied Physics and COMP Center of Excellence, Aalto University School of Science, FIN-00076 Aalto, Espoo, Finland Department of Physics, Box 1843, Brown University, Providence, RI 02912-1843, U.S.A.;Faculty of Physical Sciences, University of Iceland, 107 Reykjavik, Iceland, Department of Applied Physics, Aalto University School of Science, FIN-00076 Aalto, Espoo, Finland

Resume : Ge layers on silicon substrates are of great interest for the miniaturization of electronic and optoelectronic devices. However, the heteroepitaxial deposition of a Ge film directly on Si is complicated by the presence of a large lattice mismatch between Ge and Si. Dislocations forming in the film to release the induced strain can deteriorate its properties. We have identified various mechanisms for the formation of dislocations in the Ge film using computer simulations combining the nudged elastic band method and heredity transformations used in a genetic algorithm. The Stillinger-Weber potential is used to describe the atomic interactions. Our simulations show that the orientation of the threading arms of a 60? dislocation is dependent on the film strain. At low strain, both threading arms are screw dislocations whereas at high strain the two threading arms have different orientations with the two arms belonging to distinct (111) glide planes. As a consequence, at high strain, a 60? dislocation nucleates as a ?broken? half-loop with both ends of the half loop gliding in perpendicular directions in different glide planes. We furthermore show that this change of orientation influences the formation mechanism of 90? dislocations. An understanding of the formation mechanism of dislocations could help design procedures for growing strain released Ge films on Si with a low density of threading dislocations.

O.4.4.3
17:00
Authors : K. Wostyn (1), D. Rondas (1), R. Loo (1), S.K. Dhayalan (1), A. Hikavyy (1), A. Pacco (1), W. Elskens (1), A. Vyncke (1), P.W. Mertens (1), F. Holsteyns (1), S. De Gendt (1), T. Masaoka (2), N. Gan (2), H. Tokoshima (2), H. Morita(2), Y. Yoshida (3), A. Iwasaki (3), M. Sato (4), G. Bast (5), G. Simpson (5), N. Ulea (6)
Affiliations : (1) imec vzw, Kapeldreef 75, 3001 Leuven, Belgium (2) Kurita Water Industries Ltd., Nogi-machi, Shimotsuga-gun, Tochigi, 329-0105 Japan; (3) SCREEN Semiconductor Solutions Co. Ltd. – imec building 4 – Kapeldreef 75, 3001 Leuven, Belgium; (4) SCREEN Semiconductor Solutions Co. Ltd., 480-1 Takamiya, Hikone, Shiga, 522-0292 Japan; (5) KLA-Tencor, Parc de Busserolles, 32bis, chemin du Vieux Chêne, 38240 Meylan, France; (6) KLA-Tencor, One Technology Drive, Milpitas, CA 95035, USA

Resume : The growth of a high quality epitaxial layer requires a clean starting surface. In the case of epitaxy on a Si or Si1-xGex, optimization of the pre-epi clean sequence focuses on reducing interfacial O. The combination of a wet HF-last process with a high T (T ≥ 800˚C) H2 bake achieves these requirements. However the implementation of this pre-epi clean sequence in a CMOS integration scheme is limited due to integration-driven thermal-budget constraints, reflow and/or relaxation of advanced channel materials. The use of a low-thermal-budget (T ≤ 600˚C) in-situ GeH4-HCl clean has been proposed as an alternative to a high temperature H2 bake for Si and Si1-xGex. In this paper we will show how the wet HF and GeH4-HCl in-situ clean sequence depends on the water quality used during HF last processing. The HF solution was prepared by point-of-use mixing of HF and water. The ultra-pure water as provided by the facilities was used as such or has been further purified in a Kurita functional water unit. The HF last process performance has been evaluated for defects ≥ 21nm or compared by growing an 80nm Si0.8Ge0.2 layer on a Si substrate. In-situ treatments prior to Si0.8Ge0.2 epitaxial growth consisted of GeH4-assisted HCl etching or a H2 bake. Epitaxial quality has been quantified by surface light scattering. Using these techniques we will show how the functional water unit improves the epitaxial quality.

O.4.4.4
17:15
Authors : G. A. Chahine, J. Hilhorst, S. J. Leake, P. Boesecke, H. Djazouli, M. Elzo, M-I. Richard, G. Bussone, R. Grifone, and T. U.Schülli
Affiliations : European Synchrotron Radiation Facility, BP 220, F-38043, cedex, Grenoble, France

Resume : X-ray diffraction plays an important role in the analysis of strain, texture and epitaxial relation. Traditionally x-ray diffraction is considered as a method with poor spatial resolution yielding only spatial averages as useful results. Very recent developments in the use of highly focused beams produced on the most advanced synchrotron sources show however a great and rapidly developing potential of diffraction imaging techniques. At the ESRF Grenoble, ID01 is the beamline specialized on nanodiffraction imaging using scanning probe- and full-field techniques. Offering scanning diffraction microscopy at 100Hz with 100nm focused x-ray beams [1], full field x-ray diffraction microscopy using compound refractive lenses [2] and coherent beams for coherent diffractive imaging applications [3] we can supply a vast spectrum of techniques for high resolution strain imaging. Brought to maturity during the first phase of the ESRF upgrade these techniques allow for strain and texture imaging in thin films with a spatial resolution of 100 nm and strain sensitivity of =a/a<10-5 . The talk will give an overview on the state of the art of the nano diffraction imaging techniques readily available at ID01 and their typical field of applications today and in the near future. 1] G. A. Chahine, M.H. Zoellner, M-I. Richard, S. Guha, C. Reich, P. Zaumseil, G. Capellini, T. Schroeder and T. U. Schülli, Applied Physics Letters, 106, 071902 (2015). [2] J. Hilhorst, F. Marschall, T.N. Tran Thi, A. Last and T. U. Schulli, J. Appl. Cryst. 47, 1882-1888. (2014). [3] S. T. Haag, M-I. Richard, U. Welzel, V. Favre-Nicolin, O. Balmes, G. Richter, E. Mittemeijer and O. Thomas, Nano Lett., 13 (5), 1883–1889 (2013)

O.4.4.5
Start atSubject View AllNum.
 
Functional Oxides I : Roger Loo
09:00
Authors : S. Fathpour 1,2, A. Rao 1, P. Rabiei 3, A. Patil 3, S. Novak 1,4, K. Richardson 1,4, J. Chiles 1, and M. Malinowski 1
Affiliations : 1 CREOL, The College of Optics and Photonics, University of Central Florida, Orlando, Florida 32816, USA 2 Department of Electrical and Computer Engineering, University of Central Florida, Orlando, Florida 32816, USA 3 Partow Technologies LLC, Orlando, Florida 32816, USA 4 School of Materials Science and Engineering, COMSET, Clemson University, Clemson, South Carolina 29634, USA

Resume : Silicon photonics has been aggressively pursued in the last two decades as an integrated platform to merge optics and electronics on the same chip. However, not all photonic functionalities can be conveniently realized on silicon, e.g., lasers. Furthermore, on some of the functionalities that can be realized, the performance of the devices are not as great as those on other platforms. For instance, silicon lacks electrooptic effect for optical modulation. Alternatively, the free-carrier plasma effect has been exploited to realize optical modulators. However, such silicon optical modulators are not well-poised for high-performance optical interconnect applications due to their low extinction ratio. The traditional lithium niobate electrooptic modulators, on the other hand, have higher performance in terms of extinction ratio and very high modulation bandwidth, but suffer from large footprint, high power, difficulty of etching to form ridge waveguides and lack of integrability with silicon photonics. To address these shortcomings, submicron thin films of lithium niobate are heterogeneously integrated onto oxidized silicon substrates. To form optical waveguides, the lithium niobate thin films are loaded with index-matched materials (e.g., Ta2O5 dielectric ?or Ge23Sb7S70 chalcogenide glass). Strongly confined single-mode lithium-niobate-on-silicon microring modulators with grating couplers, and Mach-Zehnder modulators in the telecommunication C band (~ 1550 nm wavelength) are accordingly demonstrated. This heterogeneous platform on silicon substrates yields a significant improvement in extinction ratio over all-silicon modulators, and maintains a device footprint much smaller than conventional lithium niobate modulators. This is a key step to enabling high-performance dense on-chip integration, a key requirement for components of short reach optical interconnects, and higher-order advanced modulation schemes.

O.6.1.1
09:30
Authors : Felix Eltes(1), Stefan Abel(1), Florian Fallegger(1), Thilo Stöferle(1), Daniele Caimi(1), Lukas Czornomaz(1), Marta D. Rossell(2), Rolf Erni(2), Marilyne Sousa(1), Bert J. Offrein(1), Jean Fompeyrine(1)
Affiliations : (1) IBM Research GmbH, Säumerstrasse 4, CH-8803, Rüschlikon; (2) Electron Microscopy Center, Empa, Swiss Federal Laboratories for Materials Science andTechnology, 8600 Dübendorf, Switzerland

Resume : Barium titanate (BTO) is a promising example for the successful integration of an electro-optical (EO) material with a strong Pockels coefficient on silicon. Active devices utilizing the EO effect in BTO have been demonstrated showing that it can be used for EO modulation in silicon photonics. However, the demonstrated devices suffer from high optical propagation losses (44 dB/cm), which limits the performance compared to state of the art silicon photonics devices (<5 dB/cm). We report on a systematic investigation of the origin of the propagation losses in hybrid BTO/silicon waveguides: SiO2-strip-loaded waveguides fabricated on BTO layers deposited on SOI (silicon-on-insulator) substrates by molecular-beam epitaxy showed no significant absorption at a wavelength of 1550 nm. However, propagation losses increased to ~20 dB/cm in Si/BTO/SOI slot waveguide structures. Such structures are required to enhance the optical confinement in the BTO layer in active devices. We could attribute the higher propagation losses to absorption in the BTO layer induced by the reducing atmosphere during integration of the upper silicon layer. Post-deposition annealing in different gas environments confirmed this observation. Strongly oxidizing environments can be applied to lower the propagation losses to <10 dB/cm, comparable to current silicon photonics technology. Our results in obtaining low-loss BTO/Si hybrid waveguides represent a major step towards a novel integrated photonics platform.

O.6.1.2
09:45
Authors : Florencio Sanchez
Affiliations : Institut de Ciencia de Materials de Barcelona (ICMAB-CSIC), campus de la UAB, Bellaterra E-08193, Spain

Resume : Crystalline oxide buffer layers permit the growth of functional complex oxides on silicon with properties close to those of films on perovskites. I will review our progress on the integration of ferromagnetic CoFe2O4 (CFO) and ferroelectric BaTiO3 (BTO). Ferrimagnetic CFO was grown epitaxially on Si(001) and Si(111) buffered with yttria-stabilized zirconia and bixbyte (Sc2O3 and Y2O3), respectively. In the latter case, where the lattice mismatch is huge, we discuss on the epitaxial mechanisms. The stability of the interface between the used buffer layers and silicon is compared. Ferroelectric BTO was integrated on Si(001) using a LaNiO3/CeO2/YSZ buffer layer that induces compressive epitaxial stress favoring c-orientation with high ferroelectric polarization along the out-of-plane direction. The ferroelectric properties, including polarization loops and fatigue measurements, of BTO films and CFO/BTO bilayers are discussed.

O.6.1.4
10:15
Authors : Kristy J. Kormondy (1), Stefan Abel (2), Florian Fallegger (2), Youri Popoff (2), Agham B. Posadas (1), Steffen Reidt (2), Daniele Caimi (2), Marilyne Sousa (2), Marta D. Rossell (3), Chiara Marchiori (2), Jean Fompeyrine (2), and Alexander A. Demkov (1)
Affiliations : (1) Department of Physics, The University of Texas at Austin, Austin, Texas, 78712, USA; (2) IBM Research GmbH, Säumerstrasse 4, CH-8803 Rüschlikon; (3) Electron Microscopy Center, Empa, Swiss Federal Laboratories for Materials Science andTechnology, 8600 Dübendorf, Switzerland

Resume : The recent realization of electro-optic (EO) devices based on the Pockels effect in BaTiO3 (BTO) thin films on Si motivates further development of the ferroelectric oxide. Due to the challenges presented by epitaxial integration of oxides on semiconductors, molecular beam epitaxy (MBE) has been the primary deposition method for EO-active BTO films on Si. Meanwhile, alternative deposition methods (including rf sputtering, pulsed laser deposition (PLD), and atomic layer deposition), offer advantages of thermal budget and scalability. While sputtering directly on Si yields polycrystalline BTO, epitaxial BTO is obtained by first depositing a 4 nm-thick SrTiO3 (STO) buffer layer by MBE prior to subsequent BTO deposition. X-ray diffraction confirms rocking curve widths as low as 0.5° for MBE-, 0.7° for PLD-, and 2° for sputtered-BTO on STO-buffered Si. By analysing induced rotation of the polarization of a laser beam transmitted through lithographically defined electrodes, a linear EO response was verified for all crystalline BTO films. However, microscopy indicates potential sources of disorder, including porosity and variations in film morphology. Accordingly, effective Pockels coefficients of 105, 18, and 2 pm/V are measured for MBE-, sputtered-, and PLD-BTO, respectively. These results indicate the strong influence of BTO structure on EO response, an understanding necessary to fully exploit the Pockels effect in BTO for future applications in Si nanophotonics.

O.6.1.3
10:30 Coffee break    
 
Functional Oxides II : Florencio Sanchez
11:00
Authors : Hao Jiang, Can Li, and Qiangfei Xia
Affiliations : Nanodevices and Integrated Systems Lab, Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003, USA

Resume : Memristor is one of the leading contenders among the emerging post-CMOS devices. As totally replacing CMOS transistors in ICs will likely never happen, CMOS/memristor hybrid systems leverage the mature IC infrastructure and computational power of modern CMOS, while also taking advantage of novel properties and unique functionalities of memristive devices. Transition metal oxides, perovskites, and solid state electrolytes are the popular switching materials for memristive devices, but most of these materials and electrodes are not widely used in IC industry. Consequently, using materials/processes that are common in IC industry are critical for both memory and logic applications. In this talk, we will highlight our recent progress in memristive device engineering using CMOS compatible materials. Three types of devices based on HfO2, Ta doped SiO2 and SiO2 with silicon electrodes will be presented. The HfO2 devices fabricated in our lab exhibited low-voltage repeatable switching behavior with record endurance (100 billion cycles for HfO2) and extremely long data retention time (extrapolated >>10 years at 85 oC). Furthermore, the device can be programmed to multiple intermediate states that have excellent retention properties both at room temperature and at 150 oC. We also achieved reliable bipolar resistive switching from Ta-doped SiO2 with very high endurance (3×10^8 cycles). We further adopted a 3-dimensional (3D) vertical structure for our devices, a promising approach to achieve ultra-high bit density. Finally, towards even better CMOS compatibility, we developed devices with p-Si/SiO2/n-Si geometry. With a thin layer of SiO2 sandwiched between two single crystalline silicon electrodes, this device exhibits self-rectifying IV characteristics with about 10^4 rectification ratio, which is a result of an in-situ p-n junction formed at each cell in the ON state. The self-rectifying effect greatly mitigates the so-called ‘sneak path’ problem in a crossbar array, and could eventually enable massively parallel crossbar device arrays without extra selector devices.

O.6.2.1
11:15
Authors : S. U. Sharath1, S. Vogel1, E. Hildebrandt1, J. Kurian1, P. Komissinskiy1, C. Walczyk2, P. Calka2, G.Niu2, T. Schroeder2 and L. Alff1
Affiliations : 1 Institute of Materials Science, TU Darmstadt, Darmstadt, Germany 2 IHP Microelectronics, Frankfurt (Oder), Germany

Resume : Resistive Random Access Memory (RRAM) devices based on resistive switching in hafnium oxide is being investigated extensively as emerging embedded nonvolatile memories. Oxygen engineering in hafnium oxide (HfO2) thin films has been achieved using strongly oxygen deficient growth parameters, stabilizing oxygen vacancy concentrations far beyond the thermodynamical equilibrium. It was found that the conductivity of hafnium oxide grown on c-cut sapphire substrates could be tuned in a wide range by varying the oxygen flow and undergoes a metal-insulator transition1. Thin films of hafnium oxide grown on epitaxial TiN(001)/Si(001) substrates with thicknesses of 20 nm crystallize in a monoclinic symmetry (m-HfO2) at higher oxidation conditions, whereas the oxygen deficient hafnium oxide films showed an oxygen vacancy stabilized tetragonal like phase of hafnium oxide (t-HfO2-x)2. A large concentration of oxygen vacancies lead to a defect band at the Fermi-level as observed by XPS. The electrical switching measurements show that the forming voltage is suppressed for oxygen deficient films paving the way for low power devices in future2. Our study suggests that the combination of oxygen deficient and stoichiometric layers of hafnium oxide with varying thicknesses can lead to forming free devices. [1] E. Hildebrandt et. al. Appl. Phys. Lett. 99, 112902 (2011). [2] S. U. Sharath et al. Appl. Phys. Lett. 104, 063502 (2014); Appl. Phys. Lett. 105, 073505 (2014).

O.6.2.2
11:30
Authors : J.M. Vila-Fungueiriño1, R. Bachelet2, G. Saint-Girons2, R. Moalla2, B. Rivas-Murias1, M. Gich3, J.Gazquez3, G.L. Drisko4, C. Sanchez4, J. Rodriguez-Carvajal5, F. Rivadulla1, A. Carretero-Genevrier2
Affiliations : 1Centro de Investigación en Química Biológica y Materiales Moleculares (CIQUS), Universidad de Santiago de Compostela, 15782-Santiago de Compostela, Spain.. 2 INL, Institut des Nanotechnologies de Lyon, France2 3Institut de Ciència de Materials de Barcelona ICMAB, Consejo Superior de Investigaciones Científicas CSIC, Campus UAB 08193 Bellaterra, Catalonia, Spain 4UPMC-Collège de France-CNRS 7574. Collège de France, 11 place Marcelin Berthelot, 75231 Paris 5 Institut Laue-Langevin, 6 rue Jules Horowitz, BP 156, 38042 Grenoble Cedex 9, France

Resume : The combination of standard wafer-scale semiconductor processing with the properties of functional oxides opens up to innovative and more efficient devices with high value applications which can be produced at large scale. In this direction, the present work used the main strategies to monolithically integrate functional oxide thin films and nanostructures on silicon: the chemical solution deposition approach (CSD) [1] and the advanced physical vapor deposition techniques such as oxide molecular beam epitaxy (MBE). Special emphasis will be placed on oxide thin films epitaxially grown on silicon using the combination of Polymer Assisted Deposition (PAD) and MBE [2]. Several examples will be presented, with a particular stress on the control of interfaces and crystallization mechanisms on epitaxial perovskite oxide thin films (La0.7Sr0.3MnO3, SrTiO3, BaTiO3…) and nanostructured piezoelectric quartz thin films on silicon [3]. This work enlightens on the potential of nanostructured oxide thin films and the combination of both chemical and physical elaboration techniques for novel oxide-based integrated devices. [1] A. Carretero-Genevrier et al. Nanoscale, 20, 892-897. (2014). [2] J.M. Vila-Fungueiriño et al. Frontiers in Physics, doi : 10.3389/fphy.2015.00038. (2015). [3] A. Carretero-Genevrier et al. Science, 20, 892-897. (2013).

O.6.2.3
11:45
Authors : R. Moalla1, N. Baboux2, G. Sebald3, B. Vilquin1, G. Saint-Girons1, R. Bachelet1
Affiliations : 1 INL-CNRS, Ecole Centrale de Lyon, Ecully, France 2 INL-CNRS, INSA de Lyon, Villeurbanne, France 3 LGEF, INSA de Lyon, Villeurbanne, France

Resume : Pyroelectric materials which couple a change in temperature to a change in electrical polarization offer possible conversion between thermal energy and electric energy [1]. They can thus be integrated in microelectronic devices, without the necessity to maintain thermal gradients like thermoelectric materials, i) for thermal energy harvesting (via the direct pyroelectric effect), and ii) for cooling applications (via the converse pyroelectric effect, so-called electrocaloric). According to the structural dependence of properties, single-crystalline pyroelectric films can provide an enhanced conversion energy efficiency with respect to bulk or polycrystalline materials [2]. In this communication, we will present the pyroelectric properties of epitaxial Pb(Zr0.52Ti0.48)O3 films grown by sol-gel process on SrTiO3(001) and buffered Si(001) substrates. In particular, we will show the impact of structural properties (domains orientation tuned by thermal mismatch) on the intrinsic pyroelectric coefficients and electrocaloric properties. Intrinsic pyroelectric coefficient can reach -450 µC.m-2.K-1 in c-oriented films. The corresponding harvested pyroelectric energy can be beyond 10 mJ.cm-3 per cycle for temperature variations of 10°C, and temperature changes of more than 10°C can be reached close to room temperature, that can address cooling applications in microelectronic devices. [1] S.B. Lang, Phys. Today 58, 31 (2005) [2] G. Sebald et al., Smart Mater. Struct. 18, (2009)

O.6.2.4
12:00
Authors : Khushabu Agrawal, Vilas S Patil, Anil G. Khairnar, A. M. Mahajan
Affiliations : Department of Electronics, North Maharashtra University, Jalgaon, Maharashtra, India-425001

Resume : Now a days, transistors made by Ge incorporated with high-k dielectrics is the good replacement for the Si transistors to serve the scaling requirement of the 22nm technology node and beyond. We have studied the electrical properties of the HfO2 oxide deposited by atomic layer deposition (ALD) on in situ nitride passivated Ge substrate. The deposited films were annealed at 400 ºC for 2 minutes in N2 ambient by using rapid thermal annealing system (AET RX6 Model). The X-ray Photoelectron spectroscopy (XPS) result confirms the formation of GeOxNy over the germanium. The Hf 4f core level spectrum confirms the oxidation state of hafnium with doublet separation energy of 1.5ev. AFM showed the smooth surface morphology of the film. The GeON layer has the thickness of 2.85 Å measured with the help of spectroscopic elipsometry. The thickness of the HfO2/GeON stack was 5.6 nm. The Pt/Ti metal electrodes were deposited by electron beam evaporation system through shadow mask and back substrate contact was formed by depositing Aluminium using thermal evaporator. The electrical study was done by analysing capacitance voltage and also the current voltage measurements. The effective charge density Qeff calculated at 1MHz frequency was 2.11×1012 cm-2. Interface trap density Dit was calculated using Hill-Colemann technique and determined to be 3.00×1012 cm-2 eV-1. Also the effect of post deposition annealing was studied on the electrical properties of the Pt/Ti/HfO2/GeON/Ge devices.

O.6.2.5
12:15
Authors : Deok-Yong Cho, Tae Jun Seok, Hyun Soo Jin, Tae Joo Park
Affiliations : Department of Physics, Chonbuk National University, Republic of Korea; Department of Materials Science & Engineering and Department of Advanced Materials Engineering, Hanyang University, Republic of Korea

Resume : We investigated the chemical states of sulfur embedded in atomic-layer-deposited (ALD) HfO2 thin films by annealing under H2S gas, using S K-edge X-ray absorption spectroscopy (XAS). Comparative studies of the H2S treatments prior to and after the HfO2 ALD on Ge substrates revealed that the valences of the S-ions were mostly -2 at the Ge/HfO2 interface, while they were mostly +6 in the HfO2 layers. The dominance of S2- at the interface can be easily understood as a consequence of filling of defects or formation of bonding toward Ge or HfO2, locally forming GeSx or HfO2-ySy, respectively, to passivate the interface. On the other hand, the prevalence of S6+ in the oxide layers is unexpected. Most plausibly, the huge valence originates from sulfate (SO4^2-) ions, implying that certain sulfates of HfO2-z(SO4)z are formed locally in the oxide layers. We observed that the leakage current density in the post-deposition-treated film is lower than that in the pre-deposition-treated one. This suggests that the sulfate ions, though their concentration might be low, can appreciably lower the defect density in the ALD HfO2 films.

O.6.2.6
12:30 Lunch break    
 
Advanced Applications : Sasan Fathpour
14:00
Authors : Cary Gunn
Affiliations : Genalyte, Inc.

Resume : Genalyte uses silicon photonics chips to perform 128 diagnostic tests from a single drop of blood in under 15 minutes. This talk will cover the optical ring resonator, which is the heart of the platform, in detail with specific attention to key performance parameters and how they impact the performance of the system. We will review the impact this technology has on test performance and attributes, and then conclude with the advantages offered to patients and physicians.

O.7.1
14:30
Authors : Kristinn B. Gylfason, Carlos Errando-Herranz, Niklas Sandström, Reza Zandi Shafagh, Wouter van der Wijngaart, and Tommy Haraldsson
Affiliations : Micro and Nanosystems, KTH Royal Institute of Technology, Stockholm, Sweden

Resume : We present a novel integration method for packaging silicon photonic sensors with polymer microfluidics, designed to be suitable for wafer-level production. The method addresses the previously unmet manufacturing challenges of matching the microfluidic footprint area to that of the photonics, and of robust bonding of microfluidic layers to biofunctionalized surfaces. We demonstrate the fabrication, in a single step, of a microfluidic layer in the recently introduced OSTE polymer, and the subsequent unassisted dry bonding of the microfluidic layer to a grating coupled silicon photonic ring resonator sensor chip. The microfluidic layer features photopatterned through holes (vias) for optical fiber probing and fluid connections, as well as molded microchannels and tube connectors, and is manufactured and subsequently bonded to a silicon sensor chip in less than 10 minutes. Combining this new microfluidic packaging method with photonic waveguide surface gratings for light coupling allows matching the size scale of microfluidics to that of current silicon photonic biosensors.

O.7.2
15:00
Authors : Julie Grollier et al
Affiliations : CNRS/Thales lab, Palaiseau, France

Resume : Thanks to the progress in Nanotechnologies and Material Science, physicists and condensed matter scientists have recently been able to build smart nano-devices with enhanced capabilities. Some of these new devices show functionalities that could be extremely interesting for bio-inspired computing. It has been demonstrated for example that some analog and tunable nano-resistors called Memristors can mimic synapses on silicon. The industry is already developing dense networks of these nano-devices for classical digital memories. It is therefore no longer a dream to envisage building bio-inspired chips based on large-scale, high density parallel networks of these advanced devices, and taking advantage of their full functionalities. In this talk, after a brief introduction on memristors nano-devices and their applications, I will focus on our work: the development of a new generation of memristors, based on purely electronic effects, the ferroelectric and spin torque memristors. I will show that, by tuning interface properties and finely engineering the dynamics of ferroelectric polarization or magnetization, we can control the response of these memristors. In particular, I will expose how, thanks to the versatility of our spintronic nano-devices, we can implement at the nano-scale a variety of functions that could be the future building blocks of high performance, low power, bio-inspired hardware.

O.7.3
15:30 Coffee break    
16:00
Authors : Subhashis Das, Rahul Kumar, Shubhankar Majumdar, Mihir Kumar Mahata, Saptarsi Ghosh, Dhrubes Biswas
Affiliations : Advanced Technology Development Centre, Indian Institute of Technology Kharagpur, Kharagpur-721302, India.

Resume : Environmental pollution due to industries is a roaring problem today. Gases and chemical waste emitted by industries can cause environmental hazards and severe health hazards to humans. Since the last decade Volatile Organic Compound sensors have captivated much interest among researchers. Acetone, one of the most volatile organic compounds, is vastly used in chemical laboratories, industries and human consumables. In industrial areas, higher acetone concentration may cause irritation of respiratory system and eye, mood swings, nausea etc. whether it is inhaled from outside ambient or produced by body itself. So monitoring of acetone level is useful for biomedical and environmental study. AlGaN/GaN heterostructure Schottky diode has been employed to detect acetone efficiently. The inherent high density two dimensional electron gas in the AlGaN/GaN interface produced due to spontaneous and piezoelectric polarization is extremely sensitive to the change in the surface states. When the sensing device is exposed to acetone, the electrostatic potential of the AlGaN surface gets modified due to the polarity of acetone. This change in potential causes the two dimensional electron gas to change and thus changes the current. The heterostructure has been grown on Si (111) substrate with AlN nucleation layer by plasma assisted molecular beam epitaxy. Metal contacts have been deposited by e-beam evaporation technique. I-V characteristics show significant sensitivity towards acetone.

O.7.4
 
THz Devices : Francesco Montalenti
16:15
Authors : D.J. Paul
Affiliations : University of Glasgow

Resume : The indirect bandgap of silicon has precluded its use to produce efficient interband light emitters and lasers. For intersubband transitions, however, indirect bandgaps do not prevent a laser being realised. III-V THz quantum cascade lasers have been demonstrated but the polar optical phonon scattering will limit such devices to low temperature operation whilst the non-polar phonons in Group IV materials should allow much higher operating temperatures. I will present our work towards realising quantum cascade lasers at THz frequencies using Si/SiGe heterostructures. Gain up to 5 cm^–1 has been realised but the waveguide losses of >25 cm^–1 still prevent a laser being realised. I will present concepts for increasing the gain above the waveguide losses and review the issues that require to be solved if a laser is to be demonstrated. I will also present recent results of using process induced stress on germanium with the aim of producing a direct bandgap material for a laser. As the indirect bandgap of germanium is only 140 meV below the direct bandgap, biaxial tensile strain above circa 2% is required for a direct bandgap sufficient for a laser. I will demonstrate high Q cavities with tensile strained Ge above 2% and review what is required to demonstrate lasing at mid-infrared wavelengths.

O.8.1
16:45
Authors : D. Sabbagh1), L. Di Gaspare1), G. Capellini1,2), M. Virgilio3), M. Ortolani4), and M. De Seta1)
Affiliations : 1)Dipartimento di Scienze, Università Roma Tre, Viale Marconi 446, 00146 Roma, Italy 2) IHP, Technologiepark 25, 15236 Frankfurt (Oder),Germany 3)Dipartimento di Fisica “E. Fermi”, Università di Pisa, largo Pontecorvo 3, 56127 Pisa, Italy 4)Dipartimento di Fisica, Università di Roma La Sapienza, P.le A. Moro 2, 00185 Roma, Italy

Resume : We present recent results on inter-subband (ISB) light absorption and carrier relaxation dynamics in n-type s-Ge/Ge0.82Si0.18 multi quantum wells (MQW) grown on SiGe/Si(001) virtual substrates. By using FTIR Spectroscopy and pump and probe measurements, we evidenced ISB absorption occurring in the 15-45 meV spectral region (3-10 THz) and featuring line-widths of =2 meV up to 300K. The experimental data were analyzed relying on a theoretical model taking into account scattering processes due to interface roughness, spatial distribution and density of ionized donors, phonons, and extended defects. We predict that line-width <1 meV and coherence time c>1 ps can be achieved. Non radiative relaxation times R>30 ps have been measured up to 130K. Moreover, we have fabricated structures based on a three-level coupled-MQW design and measured the relaxation time  using a tunable-FEL emitting at photon energies matching the two ISB transition energies 01 and 02. We found that 10 relaxation is faster than 21, featuring a relatively high relaxation time ratio of 10/21 ≈ 0.5. Based on these results, we calculated that the optical transparency threshold can be attainted for optical power density of 30 kWcm-2. This threshold value could be further reduced by an optimization of the mode confinement in a suitable optical cavity. Our results demonstrate that n-type s-Ge/Ge0.82Si0.18 MQW are a promising route towards silicon-based on-chip emitters in the THz range.

O.8.2
17:00
Authors : Nadiia Kolomiiets 1, V.V. Afanas’ev 1, S.Jayachandran 2,3, A. Delabie 2,4, M.Heyns 2,3, A. Stesmans 1
Affiliations : 1 Department of Physics and Astronomy, University of Leuven, Celestijnenlaan 200D, 3001 Leuven, Belgium; 2 Imec, Kapeldreef 75, 3001 Leuven, Belgium 3 Department of Metallurgy and Materials, KU Leuven, Castle Arenberg 44, 3001 Leuven, Belgium; 4 Department of Chemistry, University of Leuven, Celestijnenlaan 200F, 3001 Leuven, Belgium

Resume : The insertion of O monolayers (MLs) into the Si channel has recently been shown to improve both electron and hole mobility in CMOS devices (Xu, IEDM 2012; Xu, IEEE TED 2014) with a compatible Si fabrication processes for the integration. The initial explanation for the observed effect was the separation of carrier wavefunction distributions due to the O-related band edge shift resulting in reduced scattering rates. To shed some light on Si-O superlattices (SLs) electronic structure, we used internal photoemission (IPE) of electrons, which allowed a straightforward probing of electron density of states and of the band bending inside the Si-O SL region. SLs made of 1, 2 or 5 periods of one ML of O in between 25, 15, 7, 3 or ~1 nm thick Si layers were studied by using IPE from these SLs into 20-nm thick Al2O3 film deposited on top of the SL. We observed the reduction of direct optical transition intensity in Si-O SLs by decreasing the thickness of SL periods to 1 nm, indicating the Si crystalline structure distortion inside the SL. Any change of the field dependence of IPE spectral threshold indicates no effect of O MLs on the valence band (VB) energy or on the field-induced band bending inside SL w.r.t. bulk Si. Thus, we may conclude that there is no evidence of VB edge profile modification which is the pre-requisite for carrier wavefunction redistribution. The reported enhanced mobility may be explained by the effect of O – induced stress in Si, which affects the carriers effective mass. Further, electron spin resonance indicates the absence of additional Si dangling bonds in the Si-O SL with the sensitivity of 10^11 cm-2. These findings suggest that Si-O SLs enhance the carrier mobility by inducing stress in the Si channel without creating additional harmful defects.

O.8.3
17:15
Authors : Alex Burenkov, Axel Huelsmann, Juergen Lorenz
Affiliations : Fraunhofer IISB; Fraunhofer IAF; Fraunhofer IISB

Resume : The signal processing frequency in modern data processor circuits stagnates since about 10 years. The main reason for this are the signal delays in circuit interconnects. Conventional metal and dielectric-based interconnects suffer from long delay times. The signal propagation speed at chip level is much lower than the maximum possible signal processing speed of one switching element, e.g. inverter in the nano-scaled CMOS technology. When signals between the distant parts in the chip are transferred by the high frequency self-carrying waves, e. g. plasmonic waves, the signal transmission velocity can be much faster than in conventional interconnects. In this work we suggest a new scheme of signal transmission in VLSI circuits consisting of 1) electronic plasmon-based THz signal generation, 2) signal transmission as a plasmonic wave over the distances comparable with the VLSI chip size, 3) electronic signal detection after the signal transmission. An implementation of such novel interconnect system in advanced InGaAs-InAlAs-based technology is demonstrated. The plasmon generator is implemented as a high-electron-mobility transistor (HEMT) with source and drain electrodes having a special shape that is envisaged for a better reflection of plasmonic waves from both sides of the transistor active region. The signal transmission line is implemented as a 200 to 400 µm long wave guide for terahertz plasmons. The signal detector is implemented as a small size HEMT attached to the end of the wave guide. The principal functionality of the novel interconnect scheme is discussed.

O.8.4
18:00 Best Student Presentation Awards Ceremony and Reception (Main Hall)    
Start atSubject View AllNum.
09:00 Plenary Session - Main Hall    
12:30 Lunch break    
 
Light emission I : Thomas Schroeder
14:00
Authors : S.Wirths1, R. Geiger2&3, D. Stange1, N. von den Driesch1, G. Mussler1, Z. Ikonic4, J.M. Hartmann5, S. Mantl1, J. Faist3, H. Sigg2, D. Grützmacher1 and D. Buca1
Affiliations : 1 Peter Grünberg Institute 9 (PGI 9) and JARA-Fundamentals of Future Information Technologies, Forschungszentrum Juelich, Juelich, Germany; 2 Laboratory for Micro- and Nanotechnology (LMN), Paul Scherrer Institut, Villigen, Switzerland; 3 Institute for Quantum Electronics, ETH Zürich, Zürich, Switzerland; 4 Institute of Microwaves and Photonics, School of Electronic and Electrical Engineering, University of Leeds, Leeds, UK; 5 University of Grenoble Alpes, Grenoble, France & CEA, LETI, MINATEC Campus, Grenoble, France

Resume : Silicon, the foundation of today’s microelectronics, and Ge are known for their poor light emitting properties, thus, inappropriate for active light sources. The reason for this lies in the fundamental indirect bandgap nature of these elemental group IV semiconductors. Radiative electron-hole recombination requires phonon emission/absorption in order to conserve momentum resulting in low internal quantum efficiencies. The realization of an efficient group IV light source, i.e. laser, attracted lots of research interest, since optical interconnects could become feasible and replace common electrical, RC limited copper interconnects. In this contribution we present a low temperature chemical vapor deposition (CVD) growth process for high quality GeSn binary and SiGeSn ternary alloys on 200 mm Si(001) substrates using an industrial reduced pressure CVD reactor (AIXTRON Tricent®). By alloying Ge or SiGe with Sn the transition from a fundamental indirect to a direct bandgap in these group IV alloys is demonstrated by temperature dependent PL measurements. The modal gain measurements in these monocrystalline GeSn epilayers grown on Si(001) are the prerequisite for lasing. We will discuss the lasing in GeSn alloys for different Sn contents and the ways of improving the laser emission. Different resonator cavities are investigated under optical pumping and solutions towards electrical injection will be addressed.

O.9.1.1
14:30
Authors : D. Rainko1, N. von den Driesch1, S. Wirths1, D. Stange1, C. Schulte-Braucks1, A.T. Tiedemann1, G. Mussler1, J.M. Hartmann2, Z. Ikonic3, S. Mantl1, D. Grützmacher1, and D. Buca1
Affiliations : 1 Peter Grünberg Institute (PGI 9) and JARA-Fundamentals of Future Information Technologies, Forschungszentrum Juelich, 52425, Germany; 2 CEA, LETI, MINATEC Campus, F-38054 Grenoble, France; 3 Institute of Microwaves and Photonics, School of Electronic and Electrical Engineering, University of Leeds, Leeds LS2 9JT, United Kingdom

Resume : The observation of lasing action in GeSn opens a new path for monolithic integration of electronics and photonics based on Si. In this context, the incorporation of Si into GeSn and epitaxial growth of GeSn/(Si)Ge(Sn) heterostructures are essential for electrically pumped optoelectronic devices. We will discuss the electronic band structure calculations for a variety of Group IV heterostructures, including e.g. SiGeSn claddings and GeSn active layers with type I band alignment suitable for light emitting diodes and electrically pumped laser diodes. Here, Si and Sn concentrations up to 14 at.% in the cladding layer offer an effective carrier confinement with band offsets of a few hundred meV with respect to the active layer. Epitaxial growth of direct GeSn and indirect SiGeSn layers using an industry compatible AIXTRON reduced pressure CVD reactor with showerhead technology will be presented. Si2H6, Ge2H6 and SnCl4 were employed as precursors, while B2H6 and PH3 allow in-situ doping of the grown layers. Single epilayers and multi quantum well structures have been analyzed using RBS, TEM and X-Ray diffraction showing excellent layer morphology and high Sn substitutionality. Optical characterization was performed via photoluminescence and electroluminescence on both layers and pin diodes. Room temperature electroluminescence is observed for small current densities of about 50 Acm-². This demonstrates the potential of Group IV heterostructure for optoelectronics.

O.9.1.2
14:45
Authors : Jaswant S Rathore, Krista R Khiangte* , Swagata Bhunia , Sudipto Das, Rajveer S Fandan, A Laha and S Mahapatra
Affiliations : Indian Institute of Technology Bombay,Powai, Mumbai(India)-400076

Resume : The effect of ex-situ rapid thermal annealing (RTA) on the stoichiometry and relaxation characteristics of molecular-beam-epitaxy (MBE)-grown Ge1-xSnx/Ge/Si(001) epitaxial layers is reported. RTA was carried out in N2 ambient for 10 s at temperatures TA = 400 – 700 C, in steps of 100 C. High resolution X-ray diffraction (HRXRD) and atomic force microscopy (AFM) reveal that segregation sets in even for annealing at TA = 400 C. However, pronounced changes in stoichiometry occur for TA only beyond 500 C. With reducing amount of Sn in the bulk of the epilayer, a significant narrowing of the omega-width is observed, indicating annealing-induced healing of the epilayer. In AFM images, island like features appear for the entire range of TA, which are possibly related to Sn-rich agglomerates formed due to segregation. For TA above 500 C, holes start to appear on the surface, which grow bigger and deeper with increasing TA. Systematic analysis of Sn segregation and relaxation and stoichiometric changes of the bulk epilayer, based on reciprocal space mapping (RSM), energy dispersive X-ray dispersion (EDX), and X-ray photoelectron spectroscopy (XPS), will be presented. Keywords: GeSn alloy, MBE, Annealing

O.9.1.3
15:00
Authors : S. Olivier(1), S. Malhouitre(1), C. Jany(1), C. Kopp(1), G.-H. Duan(2), P. Kaspar(2), A. Le liepvre(2), A. Accard(2), D. Make(2), N. Girard(2), G. Levaufre(2), A. Shen(2), P. Charbonnier(2), F. Mallecot(2), G. de Valicourt(2), F. Lelarge(2), J.-L. Gentner(2)
Affiliations : (1) Univ. Grenoble Alpes, CEA, LETI, MINATEC campus, CEA-Grenoble, France (2) III-V Lab, Joint Lab of Alcatel-Lucent Bell Labs France, Thales Research and Technology and CEA-Leti, Palaiseau, France

Resume : The field of silicon photonics is attracting a lot of attention due to the prospect of low-cost and compact circuits that integrate photonic and microelectronic elements on a single chip. Such silicon chips have applications in optical transmitter and receiver circuits for short-distance communications as well as for long-haul optical transmissions. Silicon photonics has proven to be a successful platform for many functional elements such as low-loss waveguides, filters, multiplexers/demultiplexers, optical modulators and Ge-on-Si photodiodes. However the integration of a light source remains a key challenge in silicon photonics. Today, the most promising approach is the heterogeneous integration of III-V light sources on silicon via wafer bonding techniques. This approach exploits the highly efficient light emission properties of direct-bandgap III-V semiconductor materials and the low-loss and highly integrated passive circuitry in silicon. We used the molecular wafer bonding technique to develop hybrid widely tunable, single mode III-V/Si lasers for wavelength division multiplexing at 1.55 µm, with a tunability over 35 nm and an output power in excess of 3 mW. Robust Distributed Feedback lasers were also developed using the same bonding technique for datacenter applications at 1.31 µm.The integration of such hybrid lasers on silicon further allows for the fabrication of more complete photonic circuits such as transmitters and receivers for WDM applications.

O.9.1.4
15:30 Coffee break    
 
Light Emission II : Stephan Wirths
16:00
Authors : D. Peschka (1), M. Thomas (1), A. Glitzky (1), R. Nuernberg (1), K. Gaertner (2), M. Virgilio (3), S. Guha (4), Th. Schroeder (4), G. Capellini (4), Th. Koprucki (1)
Affiliations : (1) Weierstrass Institute Berlin, Germany; (2) ICS, Universita della Svizzera Italiana, Lugano, Switzerland; (3) Dipartimento di Fisica ”E. Fermi,” Universita` di Pisa, Italy; (4) IHP, Frankfurt (Oder), Germany

Resume : We consider a device concept for monolithically integrated edge-emitting lasers on CMOS-qualified materials based on strained germanium (Ge) microstrips. The special SiN stressor design induces an inhomogeneous (tensile) strain distribution [1] and requires lateral current injection. Microscopic calculations of the material gain for strained Ge enter two-dimensional simulations of the carrier transport and the optical field within a cross section of the device orthogonal to the optical cavity. Using fully coupled 2D optoelectronic simulations carried out with WIAS-TeSCA we study the optoelectronic performance of a Ge emitter design for two different carrier injection schemes, see [2]. In particular, we discuss the influence of the inhomogeneous strain distribution on the modal gain. An analysis of the variation of the local material gain across the Ge layer and the modal intensity demonstrates the importance of overlap engineering between material gain and modal intensity to achieve the full benefit of the higher strain. [1] G. Capellini et al. Optics Express, vol. 22, pp. 399–410 (2014). [2] D. Peschka et al., IEEE Photon. J., Vol. 7, 1502115 (2015).

O.9.2.1
16:15
Authors : M. Virgilio, G. Capellini, M. Montanari, W.M. Klesse, Y. Yamamoto, L. Zimmermann, B. Tillack, T. Schroeder
Affiliations : M. Virgilio Dip. di Fisica ?E. Fermi?, Universit? di Pisa, Largo Pontecorvo 3, 56127 Pisa, Italy and NEST, Istituto Nanoscienze-CNR, P.za San Silvestro 12, 56127 Pisa, Italy; G. Capellini, M. Montanari, W.M. Klesse, Y. Yamamoto, L. Zimmermann, B. Tillack, and T. Schroeder IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany

Resume : Tensile germanium microstrips are candidate as gaining material in Si-based light emitting devices due to the beneficial effect of the strain field on the radiative recombination rate. In particular, their geometry and their fabrication process are compatible with carrier electrical injection realizable through standard electrical via connections and with the fabrication of a simple Fabry-Perot cavity for an edge-emitting laser. In this talk, we present a thorough investigation of microstrips infrared light emission properties carried out by means of micro-photoluminescence and electro-luminescence experiments on samples featuring different tensile strain values and doping profiles. The experimental findings are interpreted in light of a numerical modeling based on multi-valley effective mass approach, taking in to account the spatial dependence of the excess carrier density and of the self-absorption effect. The theoretical modeling allowed us to quantitatively describe the observed increase of the luminescence intensity for increasing values of strain, excess carrier density, doping, and temperature.

O.9.2.2
16:30
Authors : Eric Daniel Glowacki,1 Vedran Derek,2 Niyazi Serdar Sariciftci,1 Mile Ivanda2
Affiliations : 1. Johannes Kepler University Linz, Linz Institute for Organic Solar Cells (LIOS) / Institute of Physical Chemistry, Linz, Austria 2. Center of Excellence for Advanced Materials and Sensing Devices, Research Unit for New Functional Materials, Ruđer Bošković Institute, Zagreb, Croatia

Resume : Although silicon CMOS has been the process of choice for many uses in optoelectronic industry, its use for IR sensitive optoelectronic devices is limited to below ~1100 nm by the 1.11 eV band-gap of silicon. Extending the optical sensitivity range of silicon devices up to several microns, while maintaining good sensor responsivity, short rise and fall times, and maintaining the CMOS process compatibility, would be of great importance for possible telecom or other optoelectronic uses. Heterojunction interfaces between organic thin films and silicon often show synergetic advantages regarding certain properties. We present our work on optoelectronic devices based on heterojunctions of silicon and organic thin films of hydrogen-bonded pigment tyrian purple (6,6′-dibromoindigo) formed by vacuum evaporation. Tyrian purple is an ambipolar organic semiconductor with an optical band-gap of 1,9 eV and electron and hole mobilities of 0,4 cm2/Vs, which forms rectifying junctions with p-doped silicon. Even though the band-gap of both materials in the heterojunction is relatively high, our devices show sub silicon-bandgap IR sensitivity up to 2500 nm with responsivity of ~5 mA/W in the telecom C-band. Finally, we show that micro- and nano-structuring of silicon substrates prior to vacuum evaporation of organic layer significantly improves the responsivity of hybrid silicon-organic photodiodes.

O.9.2.3
16:45
Authors : Yosuke Shimura 1;2;3 , Ashwyn Srinivasan 1;4;5, Dries Van Thourhout 4;5, Rik Van Deun 6, Marianna Pantouvaki 1, Joris Van Campenhout 1, Roger Loo 1
Affiliations : 1 Imec, Kapeldreef 75, B - 3001 Leuven, Belgium; 2 KU Leuven, Nuclear and Radiation Physics Section, Celestijnenlaan 200d - box 2418, B - 3001 Leuven, Belgium; 3 FWO Pegasus Marie Curie Fellow; 4 Photonics Research Group (INTEC), Ghent University – imec, Sint-Pietersnieuwstraat 41, B - 9000 Ghent, Belgium; 5 Center for Nano and Biophotonics (NB-Photonics), Ghent University, Sint-Pietersnieuwstraat 41, B - 9000 Ghent, Belgium; 6 L3 – Luminescent Lanthanide Lab, Department of Inorganic and Physical Chemistry, Ghent University, Krijgslaan 281 – building S3, B-9000 Ghent, Belgium

Resume : The realization of a group IV laser is of key importance for optical interconnects. The transition from an indirect to a direct band gap material is needed to achieve a high optical gain with low threshold current densities. Current approaches to fabricate a quasi-direct band gap in Ge often rely on a combination of tensile strain and a sufficiently high n-type doping. The required n-type carrier concentration is reduced by the tensile strain. Still, it is challenging to achieve a sufficiently high electrically active doping concentration. In this contribution, we first calculate the required active doping concentration as function of the tensile strain. Next, we discuss how the in-situ phosphorus doping can be increased by optimizing the CVD process conditions, especially by reducing the growth temperature while maintaining a sufficiently high growth rate. The use of a high order precursor gas, namely Ge2H6, allows to reduce the growth temperature down to 320 °C without degrading the optical material quality. The maximal achievable electrically active phosphorus concentration increases with decreasing growth temperature. An active phosphorus concentration as high as 6.2×1019 /cm3 has been measured by Hall effect measurements which is the highest among the reported concentrations for uniformly in-situ doped Ge. The increase in active doping incorporation is directly reflected in the room temperature photoluminescence intensity.

O.9.2.4

Symposium organizers
Jean FOMPEYRINEIBM Research GmbH

Sauemerstrasse 4 CH-8803 Rueschlikon Switzerland

+41(0)44 724 8387
jfo@zurich.ibm.com
Giovanni CAPELLINI Dipartimento di Scienze / Università Roma Tre

Via della Vasca Navale 84 00146 Roma Italy

+390657333429
capellini@fis.uniroma3.it
Thomas SCHROEDER Leibniz Institute for Innovative microelectronics (IHP)

Im Technologiepark 25 15236 Frankfurt (Oder) Germany

+49 / 335 / 5625 – 318
schroeder@ihp-microelectronics.com
Roger LOOIMEC

Kapeldreef 75 B 3001 Leuven Belgium

+32 16 281 404
roger.loo@imec.be