Materials for electronics and optoelectronic applications away from silicon.O
Alternative semiconductor integration in Si microelectronics: materials, techniques & app
The symposium aims to gather scientists working on monolithic heterogeneous integration to expand silicon technology. It builds on a series of symposia that attracted a steadily increasing number of attendees. This research paves the way towards highly functionalized Silicon-based microelectronics technologies that can address challenges in our societies.
Silicon is the material of choice for manufacturing integrated circuit (IC), achieving an unbeaten level of system integration. Fundamental physical limits of Si present however major stumbling blocks for miniaturization (“More Moore”) and functionalization (“More than Moore”) of Si-based ICs. In parallel though, new markets driven by societal needs – mobile & low power technologies, ultra-fast data communication, cognitive systems, biomedical application – will stem from technologies where the integration of alternative semiconductors on the mature Si technology platform will be a key differentiator.
The symposium will be devoted to highlight novel breakthrough approaches that impact monolithic heterogeneous integration on silicon CMOS, be it about fundamental materials understanding, using novel integration schemes or targeting new field of application. The focus will be first on basic materials issues related to group IV (graphene, Ge, SiGe, (Si)GeSn etc.); III-V (Arsenides, Phosphides, Antimonides, etc); and x-VI (oxides, nitrides), covering fabrication and characterization. Contributions related to innovative hetero-integration techniques (advanced hetero epitaxy, wafer bonding, microstructure printing etc.) will be encouraged. Finally, a particular attention will be given to applications demanding an interdisciplinary approach, eg cognitive technologies and biomedical or environmental sensors. The productive interaction across disciplines (eg between life science and Si technology) will be critical to exploit the combined power of CMOS enhanced with new materials. It will help materials scientists to drive the exciting transition towards higher-value Si microelectronics, supporting technology that supports society.
Hot topics to be covered by the symposium:
Materials science, fabrication and characterization:
Group IV and IIIV semiconductors:
SiGe, Ge, and (Si)GeSn heterostructures, SOI, GOI, graphene and carbon nanotubes. Arsenides, phosphides, nitrides and antimonides.
Oxides and nitrides:
Functional perovskites, ZnO, GaN and heterostructures, oxides with resistive or metal insulator transition, topological insulators, etc.
Epitaxial lateral overgrowth, patterned wafer approaches, self-assembly techniques
Layer Transfer and TSV:
Wafer bonding, microstructure printing, die to wafer etc. Through Silicon Via techniques etc..
Applications: Logic and data communication:
CMOS, high-power / frequency transistors; IR and THz lasers; modulators, photodetectors, resonators.
New computing paradigm:
Native neuromorphic devices and circuits, quantum computing and communication
Biomedical application and environmental sensors:
Convergence with microfluidics, plasmonics for SERS, gas sensors etc.
Tentative list of invited speakers:
In order to account for possible changes, the following list include a few additional speakers with respect to the final program that will be proposed
- Jean-Marc Girard (Air Liquide Advanced Materials, USA) «Advanced precursors for semiconductor processing»
- Kristel Fobelets (Imperial College Londen, UK) «Conductivity and 1/f noise in Si nanowire arrays»
- Sebastian Koelling (University of Eindhoven, The Netherlands) «Advanced semiconductor characterization using Atom Probe»
- Cary Gunn (Genalyte, USA) «Silicon based assays for biomarker and protein detection»
- Isabelle Berbezier (CNRS, France) «Group IV nanostructures»
- Douglas J. Paul (University of Glasgow, UK) «Silicon based THz systems»
- Charles Cornet (INSA Rennes, France) «InGaP integration on Si for photonics and energy»
- Bernd Witzigmann (University of Kassel, Germany) «Computational Physics of Nanowire Photonics Applications»
- Florencio Sanchez (ICMAB, Spain) «Functional Oxides on Silicon»
- Martin Kalbac (Uni Prag, Slovakei) «Graphene Research»
- Julie Grollier (CNRS-Thales, France) «Nanodevices for Cognitive Information Processing»
- Clement Merckling (IMEC, Belgium) «III-V integration on silicon for CMOS»
- Sasan Fathpour (University Central Florida, USA) «Heterogeneous Lithium Niobate Photonics on Silicon Substrates»
- Kristinn B. Gylfason (KTH, Sweden) «Silicon photonics for biosensing applications»
- Ségolène Olivier (CEA, France) «Hybrid III-V on Silicon Lasers for Photonic Integrated Circuits on Silicon»
- Stephan Wirths (Forschungszentrum Juelich, Germany) «Lasing from GeSn-based structures»
Tentative list of scientific committee members:
- D. Buca, Juelich FZ
- F. Walker, Yale
- Y.-H. Xie, UCLA
- G. Chahine, ESRF
- R. Erni, EMPA
- R. Czajka, TU Poznan
- A. Marzegalli, U Milano
- S. Takagi, U. Tokyo
- V. Sverdlov, TU Wien
- S. Spiga, MDM-CNR
- P. Davids, Sandia Nlabs
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Symposium O opening : Jean Fompeyrine
Authors : Jean Fompeyrine (1), Giovanni Capellini (2), Thomas Schroeder (3), Roger Loo (4)
Affiliations : (1) IBM Research GmbH, Zuerich Research Laboratory, Saeumerstrasse 4, CH-8803 Rueschlikon, Switzerland; (2) Dept. of Sciences, Universita Roma Tre, Viale G. Marconi 446, 00146 Roma, Italy; (3) Leibniz Institute for Innovative microelectronics (IHP), Im Technologiepark 25, 15236 Frankfurt (Oder), Germany; (4) Imec, Kapeldreef 75, B - 3001 Leuven, Belgium
Resume : Opening remarks
Nanostructures 0D : Jean Fompeyrine
Authors : Thomas David, Luc Favre, Kailang Liu, Jean-Noel Aqua, Abdelmalek Benkouider, Meher Naffouti, Marco Abbarchi, Antoine Ronda, Martiane Cabié, Thomas Nelsius, Isabelle Berbezier
Affiliations : /
Resume : The fabrication of ultra-thin Ge-rich SiGe body on Silicon On Insulator (SOI) is highly challenging for the next generation of fully depleted CMOS devices that will be implemented in microelectronic industry. Ge-rich layers (GRLs) could be fabricated using a Ge enrichment process which takes place during dry thermal oxidation of SiGe thin films. While several studies make use of the GRL for many applications, the basic mechanism at work during the enrichment process is still unclear. In this study, we address the mechanism of formation of the GRL in two different situations and we determine the major driving forces of the enrichment process. The enrichment process is examined for different strain states: a fully relaxed Si1-xGex (x=0.2) buffer layer and a strained epitaxial Si1-xGex (x=0.2) film on SOI. For the two samples, the GRLs have the same concentration x=0.5 whatever the experimental conditions and the nominal strain state are. With this systematic study, we demonstrate that the 50% Ge content is stabilised by a self-limited segregation-like process regulated by the entropic term of the formation energy which is minimum at Si0.5Ge0.5 at the expense of the elasticity driven interdiffusion. We highlight the particular role played by this 50% concentration which is stabilized up to temperatures ≤900°C. The process provides an easy and efficient way to produce planar GRLs free of dislocations with abrupt SiGe/Si interfaces and tunable thickness. These GRLs could be fashioned for the heterogeneous integration of various systems on SOI. We demonstrate the use of the process for two typical examples of SiGe/Si core-shell systems: nanowires and nanocrystals.
Authors : T. Grzela(1), G. Capellini(1), T. Schroeder(1), I.Heidemann(2), Th. Schmidt(2), J.Falta(2) and W. M. Klesse(1)
Affiliations : (1) IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany (2) Institute of Solid State Physics, University of Bremen, Otto-Hahn-Allee 1, 28359 Bremen, Germany
Resume : Germanium (Ge) and germanium-tin (GeSn) alloys have emerged as strong alternatives to silicon in post-silicon computing, owing to their superior optoelectronic properties and compatibility with conventional transistor technology. However, the ultimate success of future Ge- and GeSn technologies, such as high-current Ge-based MOSFETs or lasers, are critically linked to the development of low-resistance and thermally stable Ohmic contacts. Here, among other metal systems, nickel germanide (NiGe) has attracted significant attention, due to its relatively low electrical resistivity and low formation temperature. In this context, we present a multi-technique experimental study on the underlying physical/chemical mechanism of Ni germanide formation. By combining STM measurements with LEEM, LEED, (S)TEM-EDX and XPS we studied at the atomic level the growth and evolution of NixGey nanostructures on Ge(001). By carefully tuning the experimental parameters we compared different deposition coverages, substrate temperatures and post-anneal treatments. Starting at relatively low temperatures of 100°C we observed the formation of a continuous NixGey wetting layer, which gradually evolves to well-ordered NixGey 3D nanostructures with increasing temperature. Finally, motivated by the well-known high sensitivity of NixGey formation to impurities and defects at the Ge/Ni interface, we explored the impact of surface-stain and incorporated Sn-atoms on the nucleation of NixGey on Ge(001).
Authors : Ryoma Hayakawa *1, Kenji Higashiguchi 2,3, Kenji Matsuda 2, Toyohiro Chikyow 1 and Yutaka Wakayama 1
Affiliations : 1. International Center for Materials Nanoarchitechtonics (WPI-MANA), National Institute for Materials Science, 1-1 Namiki, Tsukuba 305-0044, Japan 2. Department of Synthetic Chemistry and Biological Chemistry, Graduate School of Engineering, Kyoto University, Katsura, Nishikyo-ku, Kyoto 615-8510, Japan 3. PRESTO, Japan Science and Technology Agency, Kawaguchi 332-0012, Japan
Resume : Single molecular devices have been promising candidates for future CMOS devices. However, the development of such molecular devices is still at the basic research stage and practical application remains a long way off. We have proposed the adoption of functional organic molecules as quantum dots in a metal-oxide-insulator (MOS) structure to integrate attractive molecular functions into current Si devices. In this presentation, we demonstrate multi-functional manipulations of carrier transports through molecules in the Si-based double tunnel junction. First, we observed resonant tunneling through various kinds of molecules. In particular, in the sample with C60, the tunneling was observed even at 280 ºC which is almost room temperature. These results show that the carrier transports via molecular dots can be controlled by molecular orbitals. As an example, we attained multilevel control of resonant tunneling by employing binary molecules of CuPc and F16CuPc. Furthermore, the adoption of diarylethene photochromic molecules enabled reversible optical switching in the resonant tunneling. These results are unique features to use molecules as quantum dots, which will allow the integration of attractive molecular functions into current CMOS devices.  R. Hayakawa et al., Adv. Funct. Mater. 21, 2933-2937 (2011).  H.-S. Seo, R. Hayakawa et al., J. Phys. Chem. C vol. 118, pp. 6467-6472 (2014).  R. Hayakawa et al., ACS Appl. Matter. Interfaces 5, 11371 (2013).
Nanostructures 1D I : Sebastian Koelling
Authors : Bernd Witzigmann
Affiliations : Computational Electronics and Photonics Group, and CINSaT, University of Kassel, Wilhelmshöher Allee 71, 34121 Kassel, Germany
Resume : High quality III-V nanowires can be grown on Silicon substrates. In this presentation, the physical principles of semiconductor nanowire arrays are discussed, with a focus on photovoltaics and solid state lighting. As analysis tools, specific physics-based numerical models for nanophotonics and nanoelectronics have been developed, which will be discussed. In particular, the three-dimensional nature of a wire array, including the substrate and the free space on top is included in the study. For the optical extraction efficiency of an LED, absorption of electromagnetic energy in the contacts and the active layers themselves, as well as re-emission (photon-recycling) are investigated. The latter is an effect that couples the electronic and the optical system. In addition, the optical density of states is analyzed and its impact on the extraction efficiency is shown. Finally, the total electro-optical efficiency of a nanowire array LED is presented and compared to state of the art thin-film LEDs. For the nanowire array solar cell, a detailed electromagnetic and electronic analysis is presented, from which fundamental rules in terms of materials choice and wire geometry will be derived. It shows that low density regular III-V nanowire arrays can reach absorptivities identical to bulk cells, with the advantage of substrate flexibility, low material consumption, and strain engineering for multi-junction cells. As outlook, III-nitride nanowire photovoltaics is discussed.
Authors : Ivano Giuntoni (1), Lutz Geelhaar (1), Jürgen Bruns (2), Klaus Petermann (2), Henning Riechert (1)
Affiliations : (1) Paul-Drude-Institut für Festkörperelektronik, Hausvogteiplatz 5-7, D-10117 Berlin, Germany (2) Technische Universität Berlin, Fachgebiet Hochfrequenztechnik, Einsteinufer 25, D-10587 Berlin, Germany
Resume : Silicon photonics is a powerful and flexible platform for the realization of compact and low-cost optoelectronic devices which could enable overcoming the bottleneck in bandwidth of electrical on-chip and chip-to-chip interconnects. However, for some key applications like light generation silicon has to be combined with III-V semiconductors exhibiting direct bandgaps. The mismatch in lattice constants can be mitigated if these materials are grown in form of vertical free-standing nanowires, since in this case strain can elastically relax at the sidewalls. We present a new concept for the optical interfacing between vertical nanowires and planar silicon waveguides based on the selective growth of nanowires which form a grating structure on top of a silicon waveguide. This grating ensures light coupling between planar silicon structures and upright standing III-V nanowires. Numerical simulations show this technique permits a light extraction from the waveguide larger than 50%. Our new integration approach allows at the same time the electrical operation of devices based on these nanowires. Potentially very fast photodiodes could be achieved, if a pn junction is implemented in the nanowires. More importantly, the proposed system can be considered as the first step towards the integration of light sources. Our concept could hence pave the way to on-chip optical interconnect systems comprising Si waveguides and III-V nanowire lasers as well as photodiodes.
Authors : I. A. Fischer, L. Augel, S. Jitpakdeebodin, T. Kropp, N. Franz, S. Fleischer, J. Schulze
Affiliations : Institute for Semiconductor Engineering, University of Stuttgart, Paffenwaldring 47, 70569 Stuttgart
Resume : Plasmonic nanoantennas are metallic nanostructures that enable the control and manipulation of optical energy in the visible and near-infrared spectrum and have been proposed as a means to enhance absorption and quantum yields for photovoltaics, for local-surface-plasmon-resonance-based biosensors and to enhance the energy efficiency of light-emitting devices. Here, we present experimental results on the enhancement of Ge PIN-photodetector efficiency by Al nanoantennas in a Complementary-Metal-Oxide-Semiconductor-compatible setup. We fabricated disk- and rod-shaped Al nanoantennas by means of electron-beam lithography and incorporated them into the passivation layer of Ge PIN-photodetectors. Under vertical illumination the influence of the nanoantennas can be seen in a wavelength-dependent increase in photocurrent that is most pronounced close to the absorption edge of Ge. We discuss the physical origins of this effect as well as how such structures can serve as a base for plasmonic biosensing applications integrated on chip.
Authors : A. Carretero-Genevrier1, Judith Oró-Solé 2, Jaume Gázquez 2, Teresa Puig 2, Xavier Obradors2, Clément Sanchez3, Etienne Ferain4, Juan Rodríguez-Carvajal5, Narcís Mestres2*
Affiliations : 1 Institut des Nanotechnologies de Lyon (INL) CNRS, 36 avenue Guy de Collongue, 69134 Ecully, France; 2 Institut de Ciència de Materials de Barcelona ICMAB-CSIC, Campus UAB 08193 Bellaterra, Spain; 3 Laboratoire Chimie de la Matière Condensée, UMR UPMC-Collège de France-CNRS 7574. Collège de France, 11 place Marcelin Berthelot, 75231 Paris, France; 4 it4ip sa, 1 avenue Jean-Etienne Lenoir, 1348 Louvain-la-Neuve, Belgium; 5 Institut Laue-Langevin, 6 rue Jules Horowitz, BP 156, 38042 Grenoble Cedex 9, France
Resume : Monolithic direct integration of functional oxide nanowires with vertically oriented crystals on a semiconductor platform is challenging due to difficulties on preserving epitaxy, crystalline phase, and composition. Here, we developed a new strategy to produce vertical epitaxial single crystalline manganese oxide based nanowires thin films with tunable composition and enhanced ferromagnetic properties on Si substrates by using a chemical solution deposition approach . The nanowire growth mechanism involves the use of track-etched nanoporous polymer templates combined with the controlled growth of quartz thin films at the Si surface, which allowed the epitaxial stabilization and crystallization of the oxide nanowires. α-quartz layers were obtained by thermally activated devitrification of the native amorphous silica surface layer assisted by a heterogeneous catalysis driven by alkaline earth cations (Sr2+, Ba2+ or Ca2+) present in the precursor solution . Therefore, the combination of soft-chemistry and epitaxial growth opens new opportunities for the effective integration of novel technological functional complex oxides nanomaterials on Si substrates . References  A. Carretero-Genevrier et al. Chem.Soc.Rev. 43, 2042 (2014)  A. Carretero-Genevrier et al. Science 340, 827 (2013)  A. Carretero-Genevrier et al. Chem. Mater. 26, 1019 (2014)
Authors : Gunther Lippert(1), Jarek Dabrowski(1), Tim Schaffus(1), Maria Carmen Asensio(4), Jose Avila(4), Jens Baringhaus(3), Ivy Colambo(5), Felix Herziger(2), Janina Maultzsch(2), Thomas Schroeder(1), Malgorzata Sowinska(1), Christoph Tegenkamp(3), Grzegorz Lupina(1)
Affiliations : (1) IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany (2) Institut für Festkörperphysik, Technische Universität Berlin, Hardenbergstr. 36, 10623 Berlin, Germany (3) Institut für Festkörperphysik, Leibniz Universität Hannover, Appelstr. 2, 30167 Hannover, Germany (4)Synchrotron SOLEIL, Saint Aubin, BP 48, 91192 Gif-sur-Yvette, France (5) I.E.M.N. Epitaxie, Av. Poincaré, BP 60069, 59652 Villeneuve d'Ascq Cedex, FRANCE
Resume : The common transfer of graphene onto a suitable substrate inherits most likely impurities and defects from the host or transfer process (1). A graphene direct growth method within the device processing line is thus desirable. For example, sublimation of Si out of SiC to synthesize graphene is suitable for SiC platforms but needs too high temperatures for Si technologies (2). The latter technology platform is, however, of central importance for mass market applications. Germanium layers on Si(001) can be covered with graphene (3) to be compatible with the mainstream Si technology requirements. The presentation will show graphene growth on Germanium covered Silicon substrates by simulations (based on supercomputer) and experiments (MBE as well as UHV-CVD). The grown graphene films were characterized by a multi-technique thin film approach including Raman, synchrotron XPS/UPS, AFM, TEM to characterize structural properties (4) Furthermore, the electrical behavior was analyzed by 4probe-STM. 1. G. Lupina et al., Residual Metallic Contamination of Transferred Chemical Vapor Deposited Graphene. ACS Nano 9, 4776 (2015/05/26, 2015). 2. E. Moreau et al., Graphene growth by molecular beam epitaxy on the carbon-face of SiC. Applied Physics Letters 97, 241907 (2010). 3. M. L. I. Pasternak, Y. Yamamoto, A. Krajewska, G. Lupina and W. Strupinski, Optimized graphene growth on Ge(100)/Si(100) substrates. "Graphene 2015" Bilbao, (2015). 4.G. Lippert et al., Graphene grown on Germanium from atomic source. Carbon 75, 104 (2014).
Authors : Aoi Tokiwa1, Keisuke Sato1, Naoki Fukata2, Kenji Hirakuri1
Affiliations : 1.Tokyo Denki University; 2.National Institute for Materials Science
Resume : Fluorescent ammonium hexafluorosilicate ((NH4)2SiF6) particles have gained attention as novel fluorescent materials, because of excellent features such as high-efficiency fluorescence and robust photostability. We have developed a new chemical approach with fruitful advantages for synthesis process of such particles. However, the obtained particles exhibit a poor property for fluorescent color, because of yellowish ocher-emission. To tune the fluorescent color, we conducted the phosphorus (P) doping into (NH4)2SiF6 particles. In this presentation, we propose a new way to fabricate the multicolor fluorescent P-doped particles. We adopted a simplified synthesis system in which only Si and P powders and nitric hydrofluoric acid solution were hermetically sealed in polymeric container. The particles having a mean diameter of approximately 1 μm were composed of (NH4)2SiF6/phosphorus oxide composites. The fluorescent color from such particles strongly depended on the P contents. The particles with P content of 0.14 at.% showed bright orange fluorescence with a peak wavelength at 610 nm under the irradiation of 365 nm-xenon lamp. As the P content in particles was increased to 1.02 at.%, the fluorescent color changed to red-light at 640 nm. Hence, our synthesis methods can provide a new chemical route for preparation of multicolor fluorescent particles. This work was partly supported by JSPS KAKENHI Grant Number 26390105.
Authors : Robert Mroczyński, Magdalena Szymańska
Affiliations : Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland
Resume : Although hafnia-based dielectric materials have already replaced thermal silicon dioxide (SiO2) or oxynitride (SiOxNy) as the gate dielectric in nowadays Ultra-Large Scale Integration (ULSI) devices, there are still many important aspects have yet to be understood for hafnium oxide materials technology and processing. Thermal stability is a critical issue since several high temperature steps may be performed after gate dielectric fabrication in particular semiconductor device technology, and thus, strongly influence electro-physical properties of dielectric layers. In this work we examine changes of the properties of hafnium oxide (HfOx) and hafnium oxynitride (HfOxNy) deposited by means of radio frequency (r.f.) reactive magnetron sputtering process after elevated temperature treatment. Possible changes in structure, composition and electrical parameters were investigated by means of spectroscopic ellipsometry (SE), scanning electron microscopy (SEM) equipped with energy dispersive spectroscopy (EDS) microanalyzer, capacitance-voltage (C-V), as well as current-voltage (I-V) measurements. In the course of this work we will try to link the electrical parameters of MOS structures with changes of the chemical composition and structure of HfOx and HfOxNy gate dielectrics. All observations and findings will be carefully examined and described in order to formulate the concluding remarks on the thermal stability of hafnia-based dielectric materials.
Authors : V.A. Skryshevsky, Yu.S. Milovanov, I.V. Gavrilchenko, S.I. Tiagulskyi, A.V. Rusavsky, P.M. Lytvyn, V.S. Lysenko, A.N. Nazarov
Affiliations : Institute of High Technologies, Taras Shevchenko National University of Kyiv, 01601 Kyiv, Ukraine Lashkaryov Institute of Semiconductor Physics NAS of Ukraine, Kyiv, 03028 Ukraine
Resume : The impedance spectroscopy, micro-Raman scattering spectroscopy and scanning Kelvin probe force microscopy (SKPFM) techniques were applied for analysis of single graphene layer deposited by CVD technique on Cu foil with subsequent transfer on SiO2/p-Si structure. Despite that Raman spectra showed the high quality of studied layers (ratio of intensities of the D and G peaks ID/IG is better than < 0.01 and the 2D to G peaks I2D/IG ≈2) two semicircles on the Nyquist curve of Ni-graphene-Ni structure suggests the existence of inhomogeneous regions. The SKPFM technique demonstrates appearance of graphene crystallite with average size about 7-10 mkm. Exposure in ethanol and acetone vapors by different degrees affects the reactive and active resistance of graphene film. Moreover, the dynamic response behavior of impedance differs in the vapor of ethanol, acetone and phenol. It ensures that impedance spectroscopy of graphene is useful tool for detection of different gases.
Authors : R. K. Savkina, A. B. Smirnov
Affiliations : V. Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine, Kiev, Ukraine
Resume : Development of multi-band detector technology is critical and remains one of the important directions for the successful development of active and passive vision. HgCdTe-based detector structure considering different semiconductor device concepts is presented. Narrow-gap HgCdTe (MCT) technologies are well developed now, and today this material is one of the basic semiconductor for photon detectors from MWIR (λ ∼ 35 μm) to LWIR (λ ∼ 814 μm) spectral range and is used in large-scale arrays with silicon CMOS readouts. Here, we describe multi-band radiation detector based on HgCdTe/Si heterostructure which exhibit sensitivity in the middle and long wavelength IR spectral range without cryogenic cooling to achieve useful performance. MCT-based heterostructure was also considered as sub-THz detector. It was observed that HgCdTe/CdTe/ZnTe/Si heterostructure exhibits photo-response under IR photoexcitation without electrical bias and amplification in MWIR region. The prototype of photovoltaic detector is also sensitive to CO2 laser radiation on the level of ~0.04 V/W at 1 mW laser beam power in focal spot. The sensitivity of MCT-based heterostructures for sub-THz radiation (the source with 140 GHz frequency was used for testing) was found after the ion beam bombardment of the sample investigated.
Authors : Tung Pham, Lisa Michez, Vinh Le Thanh
Affiliations : Aix-Marseille Université - CNRS CINaM-UMR, 13288 Marseille, France
Resume : The development of active spintronic devices requires an efficient spin injection into semiconductors, particularly into silicon or germanium. Germanium-based diluted ferromagnetic semiconductors (DMS) doped with Mn would be an ideal candidate owing to their natural impedance match to group-IV semiconductors. Since DMS thin films have shown their limit in magnetic properties, we proposed to investigate the growth of diluted GeMn quantum dots (QDs). QDs can be grown by self-assembly via Stranski-Krastanov mode. Thanks to the spin confinement effects and reduced spin-orbit interaction, it is expected that their magnetic properties can be greatly enhanced. Previous studies show that there are two main phenomena in the growth process, namely the formation of intermetallic clusters and the inter-diffusion between Si, Ge and Mn, which deteriorate their magnetic properties. Therefore, in our work, we focused on the growth of GeMn QDs at low temperature ranging from 350-500°C, which is expected to limit diffusion. Firstly, we study the growth of pure Ge on Si substrates to optimize growth parameters. Next, we study the growth of GeMn QDs with a small concentration of Mn (1-2%). Structural analyses (AFM, RHEED, and TEM) indicate that Mn incorporation in Ge does not affect the Stranski-Krastanov growth mode. However, Mn drastically modifies the surface diffusion phenomenon and the island morphology is very different to the one observed in pure Ge QDs.
Authors : Martin Wilhelm, Ayberk Caliskan, Peter Wellmann
Affiliations : Materials Department 6 (i-meet) FAU Erlangen Nürnberg Martnesstr. 7 91058 Erlangen, Germany
Resume : We have investigated the epitaxial growth of Si-Ge-C layers on (100) Si substrates for novel optoelectronic applications of group IV-semiconductors. The goal of the work is to tailor the electronic bandgap of 3C-SiC by the partial exchange of silicon by germanium. In particular, the reduction of the bandgap of 3C-SiC of 2.3 eV down to 1.8 eV using germanium would make SiGeC an ideal material to realize a tandem solar cell on silicon. As precursors, silane (SiH4), iso-butyl germanium and propane (C3H8) were applied. The substrate temperature during deposition varied between 1150 °C and 1300 °C. During deposition the layers tended to form SixGe1-x and elementary Ge and 3C-SiC phases, rather than building the ternary SiGeC compound. In general, a lower substrate temperature and a higher Ge/Se ratio favored the deposition of Ge. Although germanium exceeded a concentration of 12% in the Si-Ge-C layers, so far no targeted Ge-C bonds could be detected by Raman spectroscopy and X-ray diffraction. However, the observed formation of SixGe1-x and elementary Ge is believed to be of great importance for near infrared optoelectronic applications. The paper will present a detailed photoluminescence study of the Si-Ge-C layer structures and will discuss its applicability in optoelectronics.
Authors : B. Salem1, V. Brouzet1,2, P. Periwal1, T. Baron1, F. Bassani1, G. Ghibaudo2
Affiliations : 1 Univ. Grenoble Alpes, LTM, F-38000 Grenoble, France CNRS, LTM, F-38000 Grenoble, France 2Univ. Grenoble Alpes3bis, IMEP-LAHC, F-38000 Grenoble, France CNRS, IMEP-LAHC, F-38000 Grenoble, France
Resume : The power dissipation associated with a high off-state current (Ioff) has become one of the major problem to the further scaling of CMOS devices. In order to decrease the Ioff and the voltage supply (VDD), it will be necessary to reduce the subthreshold slope swing (SS). In fact, the conventional MOSFET has a physical limit of SS (60mV/dec at 300K) due to the thermionic conduction mechanism. To reduce the SS, various carrier injection mechanisms have been proposed. One of the most promising low energy consumption device is the Tunnel Field-Effect Transistor (TFET) to attain steep SS, low Ioff current and high on-state current to off-state current ratio at very low VDD. The TFET consists of a gated p-i-n diode in reverse bias whose carrier transport is principally governed by band-to-band tunnelling (BTBT). In this context, we present the horizontal and vertical p-Si/i-Si/n-Si1-xGex heterostructure nanowire integration, with an in situ p(Si)-i(Si)-n(Si1-xGex) doping profile on TFET device. These nanowires were elaborated by Chemical-Vapor-Deposition using Vapor-Liquid-Solid mechanism with gold as catalyst. Doping profile along the axis of the nanowire has been evidenced using scanning capacitance microscopy. We will highlight the bandgap engineering by the Germanium concentration change on the band-to-band tunneling increase, thanks to the reduction of the band gap of the source material.
Authors : H. Ferhati1, F. Djeffal1,2,* and D. Arar1
Affiliations : 1) LEA, Department of Electronics, University of Batna, Batna 05000, Algeria. 2) LEPCM, University of Batna, Batna 05000, Algeria. *) E-mail: email@example.com, firstname.lastname@example.org Tel/Fax: 0021333805494
Resume : The CMOS technology has emerged over the last years as a promising class of techniques for optoelectronic applications, due to the superior optical and electrical properties offered by this technology for both in digital as well as in analog applications. Optically controlled field effect transistors (OC-FETs) are promising devices to overcome the undesired high power dissipation and limited bandwidth effects. However, the use of uniformly doped gate presents the well-known problem of the low commutation speed and high subthreshold swing effect, which degrade the electrical performance of the device. Therefore, in order to improve the OC-FETs performance under optical excitation, new design aspects are required. Based on numerical investigation of OC-FETs, in the present paper a Gate-Engineering-based-approach to improve the submicron OC-FET electrical and optical performance is presented. In this context, I-V, voltage gain and subthreshold characteristics of the proposed design are investigated and compared with conventional OC-FET characteristics. The proposed design provides a good solution to improve the drain current and the commutation behavior for high-performance communication applications.
Authors : K. Kacha1, F. Djeffal1,2,*and H. Ferhati1
Affiliations : 1) LEA, Department of Electronics, University of Batna, Batna 05000, Algeria. 2) LEPCM, University of Batna, Batna 05000, Algeria. *) E-mail: email@example.com, firstname.lastname@example.org Tel/Fax: 0021333805494
Resume : III-V/Si-based tandem solar cells have emerged over the last years as promising candidates for space and terrestrial application due to the high efficiency, light weight and low cost potential offered by this technology. However, the problem of the high density of dislocations at the interface III-V/Si should be investigated. Therefore, new experimental, theoretical and numerical studies which capture the accurate III-V/Si-based solar cells behavior should be developed in order to build a complete and accurate III-V/Si-based solar cell model for photovoltaic applications. In this paper, we aim at highlighting the immunity behavior of the GaAs/Si heterostructure against the defects degradation. The impact of the interfacial defects on the solar cell performance has been carried out by extensive simulation using Atlas 2-D simulator and ANFIS-based computation in order to predict the device behavior under critical conditions. The developed approach can be implemented into circuit simulators such as SPICE and PC1D in order to optimize the photovoltaic circuit performances.
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Integration I : Giovanni Capellini
Authors : C. Merckling1;a, S. Jiang1;2, Z. Liu1;2, N. Waldron1, N. Collaert1, M. Heyns1;2, Z. Wang3, B. Tian3, M. Pantouvaki1, J. Van Campenhout1, D. Van Thourhout1;3, W. Vandervorst1;2, A. Thean1
Affiliations : (1) imec, Kapeldreef 75, 3001, Leuven, Belgium; (2) Katholieke Universiteit Leuven, Celestijnenlaan 200D , 3001, Leuven, Belgium; (3) Ghent University / INTEC, Sint-Pietersnieuwstraat 41, 9000, Gent, Belgium
Resume : Monolithic integration of III-V semiconductors epitaxially grown on Si substrate have been attracting much attention as building blocks for next-generation electronics and photonics due to their potential intrinsic properties. We report here on the growth of InP and related compounds on STI patterned Si wafers by Selective Area Metal-Organic Vapor Phase Epitaxy. Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds. We investigated the fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. As a conclusion, this study of III-V selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on (001) oriented Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is original and obviously confirm the potential of this heterogeneous integration option for high mobility logic devices, and photonic applications on a common Si platform.
Authors : L. Czornomaz(1), E. Uccelli(1), M. Sousa(1), V. Deshpande(1), V. Djara(1), D. Caimi(1), M. D. Rossell(2), R. Erni(2) and J. Fompeyrine(1)
Affiliations : (1)IBM Research GmbH Zürich Laboratory, Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland (2)EMPA, Electron Microscopy Center, Uberlandstrasse 129, 8600 Dübendorf, Switzerland
Resume : Heterogeneous integration of compound semiconductors on silicon is the Holy Grail for many technologies that are critical for the society today. Low power CMOS digital circuits, high performance wireless analog systems, low cost integrated photonic circuits to name a few would greatly benefit from such an innovation. Moreover, most of these applications would benefit from having the compound semiconductor layer on top of an insulator. Many approaches have been considered, taking advantage of the defect reduction in thick buffers using wafer bonding, or of defect filtering in nanoepitaxial concepts such as epitaxial lateral overgrowth or aspect ratio trapping. We report here on the demonstration of the integration of high-quality InGaAs or InP on insulator on Si substrates, using a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based on selective epitaxy, only requires the use of standard large-area silicon substrates and typical CMOS processes. Its key feature is to rely on a geometrical filtering of defects, using changes in the growth direction rather than in the dimensions of the grown crystal. It enables the fabrication of on-insulator structures starting from both bulk and SOI Si wafers. The InGaAs and InP epitaxial structures are characterized by a very low defectivity. Such substrates can fulfill the requirements of advanced CMOS nodes, as exemplified by the demonstration of short channel, gate-first, self-aligned FinFETs with excellent electrical characteristics. The device metrics are comparable to state-of-the-art InGaAs MOSFETs on Si, highlighting the potential of our approach.
Authors : F. Bassani1, R. Alcotte1, V. Gorbenko1,2, M. Billaud1,2, R. Cipro1, M. Martin1, J. Moeyaert1, S. David1, J.P. Barnes2, N. Rochas2,Y. Bogumilowicz2, H. Boutry2, N. Chauvin3, J.B. Pin4, X. Bao4, E. Sanchez4, and T. Baron1
Affiliations : 1 Univ. Grenoble Alpes, LTM, F-38000 Grenoble, France CNRS, LTM, F-38000 Grenoble, France 2 Univ. Grenoble Alpes, F-38000 Grenoble, France CEA, LETI, MINATEC Campus, F-38054 Grenoble, France 33 Institut des Nanotechnologies de Lyon (INL)-UMR5270-CNRS, INSA-Lyon, Universite de Lyon, 7 Avenue Jean Capelle, 69621 Villeurbanne, France 4 Applied Materials, 3050 Bowers Avenue, Santa Clara, California 95054, USA
Resume : The integration of III-V materials having high carrier mobility and direct band gap on silicon substrates is an important issue for future microelectronic and optoelectronic applications, and has received renewed interest in recent years. However, the epitaxy of III-V materials on Si presents many difficulties, mainly because of the large difference in lattice parameter (>4%) and the polar/non-polar character of layer/substrate interface, thereby generating numerous structural defects such as dislocations and antiphase domain boundaries (APBs) in the epitaxial layers. We will focus on our latest achievements in the growth and properties of III-As heterostructures by metal organic chemical vapor deposition on (100)-oriented Si substrates, and also on patterned substrates. The optimization of growth parameters has enabled us to obtain thin GaAs epitaxial layers on blanket Si(100) substrates free of APBs. Room temperature µPhotoluminescence and low temperature cathodoluminescence results obtained on these layers will be presented, as well as their electronic properties obtained by Hall effect measurements. Also, the selective area growth in oxide trenches provides layers of high structural and optical quality near the top of cavities, by blocking most of dislocations in the oxide walls. The physicochemical characterization of these 3D structures obtained by ToF-SIMS, in correlation with their optical properties, will be presented. The results open the path for the integration of III-As based materials on a CMOS Si platform.
Authors : Charles RENARD1, T. Moli?re1,2, N. Cherkashin3, A. Jaffr?2, L. Vincent1, J. Alvarez2, D. Mencaraglia2, D. Bouchier1
Affiliations : 1 IEF, CNRS-UMR 8622, Bat 220, Univ Paris-Sud, 91405 Orsay, France 2 GeePs, UMR 8507 CNRS, Sup?lec, Universit?s Paris VI et XI, 11 rue Joliot Curie, 91192 Gif-sur-Yvette 3 CEMES-CNRS, Universit? de Toulouse, 29 rue J. Marvig, Toulouse, 31055, France
Resume : The interest in the integration of GaAs on Si is becoming stronger each year and is guided by applications in highly active areas such as silicon-based microelectronics technologies or photovoltaic. Significant improvements have been reported for many years, thanks to selective area epitaxy of GaAs on Si substrates patterned with dielectric films. However, these layers are inappropriate for applications involving electronic transport between GaAs and Si at a large scale. To overcome these problems we have developed a technique based on the epitaxial lateral overgrowth (ELO) of micrometer scale GaAs crystals on a 0.6 nm thick SiO2 layer from nanoscale Si seeds. The nucleation from small width openings enables to avoid the emission of misfit dislocations and the formation of antiphase domains. Besides, as the thickness of the oxide interfacial layer is sufficiently thin, a tunneling current may occur and lead to interfacial conductivity between GaAs and Si. Transmission electron microscopy analyses indicate that GaAs islands are defect free and perfectly integrated with the Si substrate. Additional measurements by confocal Raman microscopy and ?-PL, confirm the good quality of epitaxial GaAs layer. Finally, conductive AFM and EBIC I-V measurements were also performed and show that the heterojunction between GaAs and Si through the thin SiO2 interfacial layer is highly conductive. These different results will be presented and discussed during the communication.
Authors : Y. Bogumilowicz1, N. Rochat1, C. Licitra1, F. Bassani2, V. Gorbenko1,2, R. Cipro2, M. Martin2, J. Moeyaert2, J.M. Hartmann1, J.P. Barnes1, J.B. Pin3, X. Bao3, E. Sanchez3, and T. Baron2
Affiliations : 1 Univ. Grenoble Alpes, F-38000 Grenoble France, CEA, LETI, MINATEC Campus, F-38054 Grenoble, France; 2 Univ. Grenoble Alpes, F-38000 Grenoble France, CNRS-LTM, F-38054 Grenoble, France; 3 Applied Materials, Santa Clara, California, United States
Resume : The integration of III-Vs on a silicon platform would bring together the better of two worlds: the high integration density, high volume, mainstream silicon technology with the high frequency, direct bandgap and wide flavor of III-V alloys, greatly extending the functionalities of tomorrows microchips. To that end, we have first of all grown on standard 300 mm Si(001) substrates rather thick (~ 1 µm) Ge layers in a group-IV RPCVD equipment (in order to accommodate the 4 % lattice mismatch between Si and GaAs). This will save costly III-V organometallic precursors and yield higher crystalline quality layers. We have then grown in an Applied Materials MOCVD tool ~ 300 nm thick GaAs layers on top of those Ge buffers. We have explored the impact of temperature, pressure, growth rate and V/III gas phase ratio on the nucleation of GaAs on Ge. With optimized growth conditions, we have obtained GaAs layers that were uniform (<2% standard deviation over the whole 300 mm wafer), smooth (<1 nm RMS AFM 5x5 µm2 roughness), nearly Anti-Phase Boundaries - free and with a threading dislocation density of a few 107 cm-2 only. Photo- and cathodo-luminescence measurements have been performed on those GaAs layers, together with high resolution X-ray diffraction. The GaAs layers were slightly tensile strained, n-type doped (diffusion of Ge atoms) and of high optical quality. A GaAs on Ge on Si approach thus seems suitable for the integration of As- and P-based III-Vs on large diameter substrates
Integration III : Clement Merckling
Authors : C. Cornet1, O. Skibitzki2, M. Bahri3, Y. Ping Wang1, P. Guillemé1, M. Da Silva1, R. Tremblay1, P. Râle4, S. Charbonnier5, P. Turban5, L. Largeau3, G. Patriarche3, L. Lombez4, Y. Dumeige1, Y. Yamamoto2, P. Zaumseil2, M. A. Schubert2, T. Rohel1, C. Levallois1, A. Letoublon1, J.-F. Guillemoles4, T. Schroeder2,6, Y. Léger1 and O. Durand1
Affiliations : 1 UMR FOTON, CNRS, INSA-Rennes, Université de Rennes 1, Enssat, F-35708 Rennes, France; 2 IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany; 3Laboratoire de Photonique et Nanostructures, CNRS UPR 20, Route de Nozay, 91460 Marcoussis, France; 4 Institut de Recherche et Développement sur l'Energie Photovoltaïque (IRDEP), UMR 7174 - CNRS-EDF-ENSCP, EDF R&D, 6 quai Watier, 78401 Chatou Cedex, France; 5 Département Matériaux Nanosciences , Institut de Physique de Rennes UMR UR1-CNRS 6251, Université de Rennes 1, F-35042 Rennes Cedex, France; 6 Brandenburgische Technische Universität Cottbus-Senftenberg, Konrad-Zuse Str. 1, 03046 Cottbus
Resume : In this communication, we report on the development of an (In)GaP platform monolithically integrated on silicon for photonics and energy. The realization of a low defect density GaP/Si(001) platform is first presented with growth developments and associated structural characterizations (synchrotron and lab XRD setup, STM and TEM): the main result being the early annihilation of antiphase domains around 10nm of the GaP/Si interface. As an illustration of the GaP/Si platform potential, three optical devices integrated on silicon will be presented: (i) a GaAsPN/GaP/Si photovoltaic solar cell for the development of a tandem architecture on silicon, (ii) an electrically-driven GaAsPN/GaP/Si light emitting diode for further laser developments and its integration with CMOS and (iii) a GaP/Si microdisk which could be potentially used for non-linear conversion and lasing. Finally, the advantages provided by the addition of indium in GaP will be discussed in terms of bandgap engineering, and carrier mobility. Preliminary results toward the development of an InGaP/SiGe/Si platform will be presented.  Y. Wang et al., J. Appl. Cryst., (in press 2015).  S. Ilahi et al., Sol. Energy Mater. Sol. Cells (in press 2015).  O. Skibitzki et al., J. Appl. Phys. 115, 103501 (2014).
Authors : R. Comyn1- 2, Y. Cordier1, V. Aimez2, H. Maher2
Affiliations : 1. CRHEA-CNRS, Rue Bernard Gregory, Valbonne, 06560, France. 2. Laboratoire Nanotechnologies Nanosystèmes (LN2)- CNRS UMI-3463, Université de Sherbrooke, 3000 Boulevard Université, Sherbrooke, J1K OA5, Québec, Canada.
Resume : In this work, we investigate the growth of GaN High Electron Mobility Transistors (HEMTs) for monolithic integration with Silicon CMOS circuits. The present CMOS-first approach relies on the ammonia-MBE growth of AlGaN/GaN heterostructures on masked Silicon substrates. The presence of CMOS devices on the wafer is a challenge that has been addressed by reducing the maximum growth temperature of (Al,Ga)N buffer materials from 920°C to 830°C without any degradation of the GaN crystal quality as assessed by X-ray diffraction. This is a noticeable difference compared to the MOCVD technique with materials grown at temperatures superior to 1000°C. In addition, we develop dielectric stacks able to withstand the large stress arising from the growth process and to eliminate the delamination issue due to the large difference in thermal expansion coefficient between GaN and Silicon. Hall effect measurements confirm the quality of the epilayers. Capacitance-voltage measurements show that the HEMT epitaxial structures provide a capacitance plateau with a sharp pinch-off behavior attesting the absence of significant contaminations. More, transistors show output characteristics in agreement with the previously assessed transport properties and reduced electrical leakage in spite of the presence of a dielectric mask on the Silicon substrate. This is a progress compared to previous local area ammonia-MBE works where buffer contamination had to be compensated with impurities like Carbon.
Integration IV : Jean-Marc Girard
Authors : Francesco Montalenti(1), Roberto Bergamaschini(1), Marco Salvalaglio(1), Rainer Backofen (2), Fabrizio Rovaris(1), Marco Albani(1), Anna Marzegalli(1), Axel Voigt (2), and Leo Miglio(1)
Affiliations : (1) (1) L-N ESS and Dipartimento di Scienza dei Materiali, Via R. Cozzi 55, 20126 Milano (Italy); (2) Institut fur Wissenschaftliches Rechnen, Technische Universitat Dresden, 01062 Dresden, Germany
Resume : Integration of different materials, such as GaAs or Ge, on Si via heteroepitaxy is nowadays a key step involved in the fabrication of a multitude of devices, some already in the market. However, full control over the different, sometimes competing phenomena taking place during deposition  has yet to be reached. Simulations can be precious in limiting the growth-parameter space to be sampled in actual experiments when searching for the desired system quality and morphology. In this work we present a continuum approach able to tackle heteroepitaxy while matching typical experimental sizes and time scales. A convenient and general description of surface-energy anisotropy is introduced  and several illustrative applications to semiconductors are described, exploiting both Phase-Field and sharp-interface approaches. Successful comparison with experiments is demonstrated for qualitatively different systems. We also discuss how to simultaneously tackle elastic and plastic relaxation. In particular, we show how the stress field associated with an assigned distribution of misfit dislocations can be computed on the fly, its contribution to the surface chemical potential deeply influencing the growth mode and/or the morphology of the growing front.  F. Montalenti, D. Scopece, and Leo Miglio, Comptes Rendus Physique 14 (7), 542-552 (2013).  M. Salvalaglio , R. Backofen , R. Bergamaschini , F. Montalenti , and Axel Voigt, Cryst. Growth Des. (2015); (DOI:10.1021/acs.cgd.5b00165)
Authors : G. A. Chahine, J. Hilhorst, S. J. Leake, P. Boesecke, H. Djazouli, M. Elzo, M-I. Richard, G. Bussone, R. Grifone, and T. U.Schülli
Affiliations : European Synchrotron Radiation Facility, BP 220, F-38043, cedex, Grenoble, France
Resume : X-ray diffraction plays an important role in the analysis of strain, texture and epitaxial relation. Traditionally x-ray diffraction is considered as a method with poor spatial resolution yielding only spatial averages as useful results. Very recent developments in the use of highly focused beams produced on the most advanced synchrotron sources show however a great and rapidly developing potential of diffraction imaging techniques. At the ESRF Grenoble, ID01 is the beamline specialized on nanodiffraction imaging using scanning probe- and full-field techniques. Offering scanning diffraction microscopy at 100Hz with 100nm focused x-ray beams , full field x-ray diffraction microscopy using compound refractive lenses  and coherent beams for coherent diffractive imaging applications  we can supply a vast spectrum of techniques for high resolution strain imaging. Brought to maturity during the first phase of the ESRF upgrade these techniques allow for strain and texture imaging in thin films with a spatial resolution of 100 nm and strain sensitivity of =a/a<10-5 . The talk will give an overview on the state of the art of the nano diffraction imaging techniques readily available at ID01 and their typical field of applications today and in the near future. 1] G. A. Chahine, M.H. Zoellner, M-I. Richard, S. Guha, C. Reich, P. Zaumseil, G. Capellini, T. Schroeder and T. U. Schülli, Applied Physics Letters, 106, 071902 (2015).  J. Hilhorst, F. Marschall, T.N. Tran Thi, A. Last and T. U. Schulli, J. Appl. Cryst. 47, 1882-1888. (2014).  S. T. Haag, M-I. Richard, U. Welzel, V. Favre-Nicolin, O. Balmes, G. Richter, E. Mittemeijer and O. Thomas, Nano Lett., 13 (5), 18831889 (2013)
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Functional Oxides I : Roger Loo
Authors : S. Fathpour 1,2, A. Rao 1, P. Rabiei 3, A. Patil 3, S. Novak 1,4, K. Richardson 1,4, J. Chiles 1, and M. Malinowski 1
Affiliations : 1 CREOL, The College of Optics and Photonics, University of Central Florida, Orlando, Florida 32816, USA 2 Department of Electrical and Computer Engineering, University of Central Florida, Orlando, Florida 32816, USA 3 Partow Technologies LLC, Orlando, Florida 32816, USA 4 School of Materials Science and Engineering, COMSET, Clemson University, Clemson, South Carolina 29634, USA
Resume : Silicon photonics has been aggressively pursued in the last two decades as an integrated platform to merge optics and electronics on the same chip. However, not all photonic functionalities can be conveniently realized on silicon, e.g., lasers. Furthermore, on some of the functionalities that can be realized, the performance of the devices are not as great as those on other platforms. For instance, silicon lacks electrooptic effect for optical modulation. Alternatively, the free-carrier plasma effect has been exploited to realize optical modulators. However, such silicon optical modulators are not well-poised for high-performance optical interconnect applications due to their low extinction ratio. The traditional lithium niobate electrooptic modulators, on the other hand, have higher performance in terms of extinction ratio and very high modulation bandwidth, but suffer from large footprint, high power, difficulty of etching to form ridge waveguides and lack of integrability with silicon photonics. To address these shortcomings, submicron thin films of lithium niobate are heterogeneously integrated onto oxidized silicon substrates. To form optical waveguides, the lithium niobate thin films are loaded with index-matched materials (e.g., Ta2O5 dielectric ?or Ge23Sb7S70 chalcogenide glass). Strongly confined single-mode lithium-niobate-on-silicon microring modulators with grating couplers, and Mach-Zehnder modulators in the telecommunication C band (~ 1550 nm wavelength) are accordingly demonstrated. This heterogeneous platform on silicon substrates yields a significant improvement in extinction ratio over all-silicon modulators, and maintains a device footprint much smaller than conventional lithium niobate modulators. This is a key step to enabling high-performance dense on-chip integration, a key requirement for components of short reach optical interconnects, and higher-order advanced modulation schemes.
Authors : Felix Eltes(1), Stefan Abel(1), Florian Fallegger(1), Thilo Stöferle(1), Daniele Caimi(1), Lukas Czornomaz(1), Marta D. Rossell(2), Rolf Erni(2), Marilyne Sousa(1), Bert J. Offrein(1), Jean Fompeyrine(1)
Affiliations : (1) IBM Research GmbH, Säumerstrasse 4, CH-8803, Rüschlikon; (2) Electron Microscopy Center, Empa, Swiss Federal Laboratories for Materials Science andTechnology, 8600 Dübendorf, Switzerland
Resume : Barium titanate (BTO) is a promising example for the successful integration of an electro-optical (EO) material with a strong Pockels coefficient on silicon. Active devices utilizing the EO effect in BTO have been demonstrated showing that it can be used for EO modulation in silicon photonics. However, the demonstrated devices suffer from high optical propagation losses (44 dB/cm), which limits the performance compared to state of the art silicon photonics devices (<5 dB/cm). We report on a systematic investigation of the origin of the propagation losses in hybrid BTO/silicon waveguides: SiO2-strip-loaded waveguides fabricated on BTO layers deposited on SOI (silicon-on-insulator) substrates by molecular-beam epitaxy showed no significant absorption at a wavelength of 1550 nm. However, propagation losses increased to ~20 dB/cm in Si/BTO/SOI slot waveguide structures. Such structures are required to enhance the optical confinement in the BTO layer in active devices. We could attribute the higher propagation losses to absorption in the BTO layer induced by the reducing atmosphere during integration of the upper silicon layer. Post-deposition annealing in different gas environments confirmed this observation. Strongly oxidizing environments can be applied to lower the propagation losses to <10 dB/cm, comparable to current silicon photonics technology. Our results in obtaining low-loss BTO/Si hybrid waveguides represent a major step towards a novel integrated photonics platform.
Authors : Florencio Sanchez
Affiliations : Institut de Ciencia de Materials de Barcelona (ICMAB-CSIC), campus de la UAB, Bellaterra E-08193, Spain
Resume : Crystalline oxide buffer layers permit the growth of functional complex oxides on silicon with properties close to those of films on perovskites. I will review our progress on the integration of ferromagnetic CoFe2O4 (CFO) and ferroelectric BaTiO3 (BTO). Ferrimagnetic CFO was grown epitaxially on Si(001) and Si(111) buffered with yttria-stabilized zirconia and bixbyte (Sc2O3 and Y2O3), respectively. In the latter case, where the lattice mismatch is huge, we discuss on the epitaxial mechanisms. The stability of the interface between the used buffer layers and silicon is compared. Ferroelectric BTO was integrated on Si(001) using a LaNiO3/CeO2/YSZ buffer layer that induces compressive epitaxial stress favoring c-orientation with high ferroelectric polarization along the out-of-plane direction. The ferroelectric properties, including polarization loops and fatigue measurements, of BTO films and CFO/BTO bilayers are discussed.
Authors : S. U. Sharath1, S. Vogel1, E. Hildebrandt1, J. Kurian1, P. Komissinskiy1, C. Walczyk2, P. Calka2, G.Niu2, T. Schroeder2 and L. Alff1
Affiliations : 1 Institute of Materials Science, TU Darmstadt, Darmstadt, Germany 2 IHP Microelectronics, Frankfurt (Oder), Germany
Resume : Resistive Random Access Memory (RRAM) devices based on resistive switching in hafnium oxide is being investigated extensively as emerging embedded nonvolatile memories. Oxygen engineering in hafnium oxide (HfO2) thin films has been achieved using strongly oxygen deficient growth parameters, stabilizing oxygen vacancy concentrations far beyond the thermodynamical equilibrium. It was found that the conductivity of hafnium oxide grown on c-cut sapphire substrates could be tuned in a wide range by varying the oxygen flow and undergoes a metal-insulator transition1. Thin films of hafnium oxide grown on epitaxial TiN(001)/Si(001) substrates with thicknesses of 20 nm crystallize in a monoclinic symmetry (m-HfO2) at higher oxidation conditions, whereas the oxygen deficient hafnium oxide films showed an oxygen vacancy stabilized tetragonal like phase of hafnium oxide (t-HfO2-x)2. A large concentration of oxygen vacancies lead to a defect band at the Fermi-level as observed by XPS. The electrical switching measurements show that the forming voltage is suppressed for oxygen deficient films paving the way for low power devices in future2. Our study suggests that the combination of oxygen deficient and stoichiometric layers of hafnium oxide with varying thicknesses can lead to forming free devices.  E. Hildebrandt et. al. Appl. Phys. Lett. 99, 112902 (2011).  S. U. Sharath et al. Appl. Phys. Lett. 104, 063502 (2014); Appl. Phys. Lett. 105, 073505 (2014).
Authors : J.M. Vila-Fungueiriño1, R. Bachelet2, G. Saint-Girons2, R. Moalla2, B. Rivas-Murias1, M. Gich3, J.Gazquez3, G.L. Drisko4, C. Sanchez4, J. Rodriguez-Carvajal5, F. Rivadulla1, A. Carretero-Genevrier2
Affiliations : 1Centro de Investigación en Química Biológica y Materiales Moleculares (CIQUS), Universidad de Santiago de Compostela, 15782-Santiago de Compostela, Spain.. 2 INL, Institut des Nanotechnologies de Lyon, France2 3Institut de Ciència de Materials de Barcelona ICMAB, Consejo Superior de Investigaciones Científicas CSIC, Campus UAB 08193 Bellaterra, Catalonia, Spain 4UPMC-Collège de France-CNRS 7574. Collège de France, 11 place Marcelin Berthelot, 75231 Paris 5 Institut Laue-Langevin, 6 rue Jules Horowitz, BP 156, 38042 Grenoble Cedex 9, France
Resume : The combination of standard wafer-scale semiconductor processing with the properties of functional oxides opens up to innovative and more efficient devices with high value applications which can be produced at large scale. In this direction, the present work used the main strategies to monolithically integrate functional oxide thin films and nanostructures on silicon: the chemical solution deposition approach (CSD)  and the advanced physical vapor deposition techniques such as oxide molecular beam epitaxy (MBE). Special emphasis will be placed on oxide thin films epitaxially grown on silicon using the combination of Polymer Assisted Deposition (PAD) and MBE . Several examples will be presented, with a particular stress on the control of interfaces and crystallization mechanisms on epitaxial perovskite oxide thin films (La0.7Sr0.3MnO3, SrTiO3, BaTiO3 ) and nanostructured piezoelectric quartz thin films on silicon . This work enlightens on the potential of nanostructured oxide thin films and the combination of both chemical and physical elaboration techniques for novel oxide-based integrated devices.  A. Carretero-Genevrier et al. Nanoscale, 20, 892-897. (2014).  J.M. Vila-Fungueiriño et al. Frontiers in Physics, doi : 10.3389/fphy.2015.00038. (2015).  A. Carretero-Genevrier et al. Science, 20, 892-897. (2013).
Authors : R. Moalla1, N. Baboux2, G. Sebald3, B. Vilquin1, G. Saint-Girons1, R. Bachelet1
Affiliations : 1 INL-CNRS, Ecole Centrale de Lyon, Ecully, France 2 INL-CNRS, INSA de Lyon, Villeurbanne, France 3 LGEF, INSA de Lyon, Villeurbanne, France
Resume : Pyroelectric materials which couple a change in temperature to a change in electrical polarization offer possible conversion between thermal energy and electric energy . They can thus be integrated in microelectronic devices, without the necessity to maintain thermal gradients like thermoelectric materials, i) for thermal energy harvesting (via the direct pyroelectric effect), and ii) for cooling applications (via the converse pyroelectric effect, so-called electrocaloric). According to the structural dependence of properties, single-crystalline pyroelectric films can provide an enhanced conversion energy efficiency with respect to bulk or polycrystalline materials . In this communication, we will present the pyroelectric properties of epitaxial Pb(Zr0.52Ti0.48)O3 films grown by sol-gel process on SrTiO3(001) and buffered Si(001) substrates. In particular, we will show the impact of structural properties (domains orientation tuned by thermal mismatch) on the intrinsic pyroelectric coefficients and electrocaloric properties. Intrinsic pyroelectric coefficient can reach -450 µC.m-2.K-1 in c-oriented films. The corresponding harvested pyroelectric energy can be beyond 10 mJ.cm-3 per cycle for temperature variations of 10°C, and temperature changes of more than 10°C can be reached close to room temperature, that can address cooling applications in microelectronic devices.  S.B. Lang, Phys. Today 58, 31 (2005)  G. Sebald et al., Smart Mater. Struct. 18, (2009)
Authors : Khushabu Agrawal, Vilas S Patil, Anil G. Khairnar, A. M. Mahajan
Affiliations : Department of Electronics, North Maharashtra University, Jalgaon, Maharashtra, India-425001
Resume : Now a days, transistors made by Ge incorporated with high-k dielectrics is the good replacement for the Si transistors to serve the scaling requirement of the 22nm technology node and beyond. We have studied the electrical properties of the HfO2 oxide deposited by atomic layer deposition (ALD) on in situ nitride passivated Ge substrate. The deposited films were annealed at 400 ºC for 2 minutes in N2 ambient by using rapid thermal annealing system (AET RX6 Model). The X-ray Photoelectron spectroscopy (XPS) result confirms the formation of GeOxNy over the germanium. The Hf 4f core level spectrum confirms the oxidation state of hafnium with doublet separation energy of 1.5ev. AFM showed the smooth surface morphology of the film. The GeON layer has the thickness of 2.85 Å measured with the help of spectroscopic elipsometry. The thickness of the HfO2/GeON stack was 5.6 nm. The Pt/Ti metal electrodes were deposited by electron beam evaporation system through shadow mask and back substrate contact was formed by depositing Aluminium using thermal evaporator. The electrical study was done by analysing capacitance voltage and also the current voltage measurements. The effective charge density Qeff calculated at 1MHz frequency was 2.11×1012 cm-2. Interface trap density Dit was calculated using Hill-Colemann technique and determined to be 3.00×1012 cm-2 eV-1. Also the effect of post deposition annealing was studied on the electrical properties of the Pt/Ti/HfO2/GeON/Ge devices.
Authors : Deok-Yong Cho, Tae Jun Seok, Hyun Soo Jin, Tae Joo Park
Affiliations : Department of Physics, Chonbuk National University, Republic of Korea; Department of Materials Science & Engineering and Department of Advanced Materials Engineering, Hanyang University, Republic of Korea
Resume : We investigated the chemical states of sulfur embedded in atomic-layer-deposited (ALD) HfO2 thin films by annealing under H2S gas, using S K-edge X-ray absorption spectroscopy (XAS). Comparative studies of the H2S treatments prior to and after the HfO2 ALD on Ge substrates revealed that the valences of the S-ions were mostly -2 at the Ge/HfO2 interface, while they were mostly +6 in the HfO2 layers. The dominance of S2- at the interface can be easily understood as a consequence of filling of defects or formation of bonding toward Ge or HfO2, locally forming GeSx or HfO2-ySy, respectively, to passivate the interface. On the other hand, the prevalence of S6+ in the oxide layers is unexpected. Most plausibly, the huge valence originates from sulfate (SO4^2-) ions, implying that certain sulfates of HfO2-z(SO4)z are formed locally in the oxide layers. We observed that the leakage current density in the post-deposition-treated film is lower than that in the pre-deposition-treated one. This suggests that the sulfate ions, though their concentration might be low, can appreciably lower the defect density in the ALD HfO2 films.
Authors : D. Sabbagh1), L. Di Gaspare1), G. Capellini1,2), M. Virgilio3), M. Ortolani4), and M. De Seta1)
Affiliations : 1)Dipartimento di Scienze, Università Roma Tre, Viale Marconi 446, 00146 Roma, Italy 2) IHP, Technologiepark 25, 15236 Frankfurt (Oder),Germany 3)Dipartimento di Fisica E. Fermi, Università di Pisa, largo Pontecorvo 3, 56127 Pisa, Italy 4)Dipartimento di Fisica, Università di Roma La Sapienza, P.le A. Moro 2, 00185 Roma, Italy
Resume : We present recent results on inter-subband (ISB) light absorption and carrier relaxation dynamics in n-type s-Ge/Ge0.82Si0.18 multi quantum wells (MQW) grown on SiGe/Si(001) virtual substrates. By using FTIR Spectroscopy and pump and probe measurements, we evidenced ISB absorption occurring in the 15-45 meV spectral region (3-10 THz) and featuring line-widths of =2 meV up to 300K. The experimental data were analyzed relying on a theoretical model taking into account scattering processes due to interface roughness, spatial distribution and density of ionized donors, phonons, and extended defects. We predict that line-width <1 meV and coherence time c>1 ps can be achieved. Non radiative relaxation times R>30 ps have been measured up to 130K. Moreover, we have fabricated structures based on a three-level coupled-MQW design and measured the relaxation time using a tunable-FEL emitting at photon energies matching the two ISB transition energies 01 and 02. We found that 10 relaxation is faster than 21, featuring a relatively high relaxation time ratio of 10/21 ≈ 0.5. Based on these results, we calculated that the optical transparency threshold can be attainted for optical power density of 30 kWcm-2. This threshold value could be further reduced by an optimization of the mode confinement in a suitable optical cavity. Our results demonstrate that n-type s-Ge/Ge0.82Si0.18 MQW are a promising route towards silicon-based on-chip emitters in the THz range.
Authors : Nadiia Kolomiiets 1, V.V. Afanasev 1, S.Jayachandran 2,3, A. Delabie 2,4, M.Heyns 2,3, A. Stesmans 1
Affiliations : 1 Department of Physics and Astronomy, University of Leuven, Celestijnenlaan 200D, 3001 Leuven, Belgium; 2 Imec, Kapeldreef 75, 3001 Leuven, Belgium 3 Department of Metallurgy and Materials, KU Leuven, Castle Arenberg 44, 3001 Leuven, Belgium; 4 Department of Chemistry, University of Leuven, Celestijnenlaan 200F, 3001 Leuven, Belgium
Resume : The insertion of O monolayers (MLs) into the Si channel has recently been shown to improve both electron and hole mobility in CMOS devices (Xu, IEDM 2012; Xu, IEEE TED 2014) with a compatible Si fabrication processes for the integration. The initial explanation for the observed effect was the separation of carrier wavefunction distributions due to the O-related band edge shift resulting in reduced scattering rates. To shed some light on Si-O superlattices (SLs) electronic structure, we used internal photoemission (IPE) of electrons, which allowed a straightforward probing of electron density of states and of the band bending inside the Si-O SL region. SLs made of 1, 2 or 5 periods of one ML of O in between 25, 15, 7, 3 or ~1 nm thick Si layers were studied by using IPE from these SLs into 20-nm thick Al2O3 film deposited on top of the SL. We observed the reduction of direct optical transition intensity in Si-O SLs by decreasing the thickness of SL periods to 1 nm, indicating the Si crystalline structure distortion inside the SL. Any change of the field dependence of IPE spectral threshold indicates no effect of O MLs on the valence band (VB) energy or on the field-induced band bending inside SL w.r.t. bulk Si. Thus, we may conclude that there is no evidence of VB edge profile modification which is the pre-requisite for carrier wavefunction redistribution. The reported enhanced mobility may be explained by the effect of O induced stress in Si, which affects the carriers effective mass. Further, electron spin resonance indicates the absence of additional Si dangling bonds in the Si-O SL with the sensitivity of 10^11 cm-2. These findings suggest that Si-O SLs enhance the carrier mobility by inducing stress in the Si channel without creating additional harmful defects.
Authors : Alex Burenkov, Axel Huelsmann, Juergen Lorenz
Affiliations : Fraunhofer IISB; Fraunhofer IAF; Fraunhofer IISB
Resume : The signal processing frequency in modern data processor circuits stagnates since about 10 years. The main reason for this are the signal delays in circuit interconnects. Conventional metal and dielectric-based interconnects suffer from long delay times. The signal propagation speed at chip level is much lower than the maximum possible signal processing speed of one switching element, e.g. inverter in the nano-scaled CMOS technology. When signals between the distant parts in the chip are transferred by the high frequency self-carrying waves, e. g. plasmonic waves, the signal transmission velocity can be much faster than in conventional interconnects. In this work we suggest a new scheme of signal transmission in VLSI circuits consisting of 1) electronic plasmon-based THz signal generation, 2) signal transmission as a plasmonic wave over the distances comparable with the VLSI chip size, 3) electronic signal detection after the signal transmission. An implementation of such novel interconnect system in advanced InGaAs-InAlAs-based technology is demonstrated. The plasmon generator is implemented as a high-electron-mobility transistor (HEMT) with source and drain electrodes having a special shape that is envisaged for a better reflection of plasmonic waves from both sides of the transistor active region. The signal transmission line is implemented as a 200 to 400 µm long wave guide for terahertz plasmons. The signal detector is implemented as a small size HEMT attached to the end of the wave guide. The principal functionality of the novel interconnect scheme is discussed.
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Authors : D. Rainko1, N. von den Driesch1, S. Wirths1, D. Stange1, C. Schulte-Braucks1, A.T. Tiedemann1, G. Mussler1, J.M. Hartmann2, Z. Ikonic3, S. Mantl1, D. Grützmacher1, and D. Buca1
Affiliations : 1 Peter Grünberg Institute (PGI 9) and JARA-Fundamentals of Future Information Technologies, Forschungszentrum Juelich, 52425, Germany; 2 CEA, LETI, MINATEC Campus, F-38054 Grenoble, France; 3 Institute of Microwaves and Photonics, School of Electronic and Electrical Engineering, University of Leeds, Leeds LS2 9JT, United Kingdom
Resume : The observation of lasing action in GeSn opens a new path for monolithic integration of electronics and photonics based on Si. In this context, the incorporation of Si into GeSn and epitaxial growth of GeSn/(Si)Ge(Sn) heterostructures are essential for electrically pumped optoelectronic devices. We will discuss the electronic band structure calculations for a variety of Group IV heterostructures, including e.g. SiGeSn claddings and GeSn active layers with type I band alignment suitable for light emitting diodes and electrically pumped laser diodes. Here, Si and Sn concentrations up to 14 at.% in the cladding layer offer an effective carrier confinement with band offsets of a few hundred meV with respect to the active layer. Epitaxial growth of direct GeSn and indirect SiGeSn layers using an industry compatible AIXTRON reduced pressure CVD reactor with showerhead technology will be presented. Si2H6, Ge2H6 and SnCl4 were employed as precursors, while B2H6 and PH3 allow in-situ doping of the grown layers. Single epilayers and multi quantum well structures have been analyzed using RBS, TEM and X-Ray diffraction showing excellent layer morphology and high Sn substitutionality. Optical characterization was performed via photoluminescence and electroluminescence on both layers and pin diodes. Room temperature electroluminescence is observed for small current densities of about 50 Acm-². This demonstrates the potential of Group IV heterostructure for optoelectronics.
Authors : Eric Daniel Glowacki,1 Vedran Derek,2 Niyazi Serdar Sariciftci,1 Mile Ivanda2
Affiliations : 1. Johannes Kepler University Linz, Linz Institute for Organic Solar Cells (LIOS) / Institute of Physical Chemistry, Linz, Austria 2. Center of Excellence for Advanced Materials and Sensing Devices, Research Unit for New Functional Materials, Ruđer Boković Institute, Zagreb, Croatia
Resume : Although silicon CMOS has been the process of choice for many uses in optoelectronic industry, its use for IR sensitive optoelectronic devices is limited to below ~1100 nm by the 1.11 eV band-gap of silicon. Extending the optical sensitivity range of silicon devices up to several microns, while maintaining good sensor responsivity, short rise and fall times, and maintaining the CMOS process compatibility, would be of great importance for possible telecom or other optoelectronic uses. Heterojunction interfaces between organic thin films and silicon often show synergetic advantages regarding certain properties. We present our work on optoelectronic devices based on heterojunctions of silicon and organic thin films of hydrogen-bonded pigment tyrian purple (6,6′-dibromoindigo) formed by vacuum evaporation. Tyrian purple is an ambipolar organic semiconductor with an optical band-gap of 1,9 eV and electron and hole mobilities of 0,4 cm2/Vs, which forms rectifying junctions with p-doped silicon. Even though the band-gap of both materials in the heterojunction is relatively high, our devices show sub silicon-bandgap IR sensitivity up to 2500 nm with responsivity of ~5 mA/W in the telecom C-band. Finally, we show that micro- and nano-structuring of silicon substrates prior to vacuum evaporation of organic layer significantly improves the responsivity of hybrid silicon-organic photodiodes.
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