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2014 Fall Meeting

SEMICONDUCTOR MATERIALS AND SPINTRONICS

J

Alternative semiconductor integration in Si microelectronics

The symposium is a follow-up of the very successful symposium A organized at the E-MRS Fall Meeting 2013. It is devoted to highlight breakthroughs in the field of alternative semiconductor integration on the mature Silicon technology platform. This research area paves the way towards high performing (More Moore) and / or highly functionalized (More than Moore) Silicon-based microelectronics technologies that will address challenges in modern societies.

Scope:

Over the past 50 years, Silicon (Si) became the predominant material of choice for manufacturing integrated circuit (IC) technologies, achieving an unbeaten level of system integration. However, fundamental physical limits of Si present major stumbling blocks for further miniaturization ("More Moore") and/or functionalization (" More than Moore" ) of Si ICs. Future microelectronics applications for society (such as: low-power electronics for green technologies, merging of photonics & electronics for ultra-fast data communication, biomedical systems for aging society etc.) are thus the driving forces for the integration of alternative semiconductors on the mature Si technology platform.

The symposium will be devoted to highlight novel breakthrough approaches in terms of materials science (group IV (graphene, Ge, SiGe, (Si)GeSn etc.) ; III-V (Arsenides, Phosphides, Nitrides etc) ; II-VI (ZnO etc.)), semiconducting oxides etc.), advanced material characterization, hetero-integration techniques (advanced hetero epitaxy, wafer bonding, microstructure printing etc.) and innovative hybrid technologies (optoelectronics, high mobility CMOS, universal memories, biomedical sensors etc.). It is by the productive interaction of "More Moore" (i.e. increase of CMOS circuitry computing power) and "More than Moore" (i.e. diversification of Si circuitries) approaches that materials scientists drive today the exciting transition towards higher-value Si microelectronics, from supporting technology towards supporting society.

Hot topics to be covered by the symposium

Materials science:
Group IV semiconductors:
SiGe, Ge, and (Si)GeSn heterostructures, SOI, GOI, graphene and carbon nanotubes.
III-V semiconductors:

Arsenides, phosphides, nitrides and antimonides
Semiconducting oxides:

ZnO, high electron mobility heterostructures, topological insulators, etc.
Advanced Material Characterization

Synchrotron based characterization, transmission electron microscopy, optical spectroscopy, scanning probe techniques, in-situ characterization, etc

Integration Techniques:
Advanced heteroepitaxy:

Epitaxial lateral overgrowth, patterned wafer approaches, self-assembly techniques
Layer Transfer:

Wafer bonding, microstructure printing, die to wafer etc.
Heterointegration:

Through Silicon Via techniques etc.

Applications:
Logics:

CMOS high - mobility channels (Ge & III-V), SiGe & III-V high-power / frequency transistors;
Photonics:

III-V & Ge based IR and THz lasers; modulators, photodetectors, resonators etc.
Sensors:

Biomedical applications, gas sensors etc.

Student awards:

A number of student awards are available to honor and encourage young scientists whose academic achievements and current research display a high level of excellence and distinction.The awardees should be the main author of a manuscript and must be entrusted with the presentation of the paper. The winners will be selected during the conference by the members of the organization and scientific committee as well as by invited speakers.

Application (for best student award):

The applicant must submit BY EMAIL the following items to the main symposium organizer ( roger.loo@imec.be) in order to be considered for the Graduate Student Award competition:
- A short descripition of work associated with the abstract to be considered (max 300 words)
- One copy of the concerned abstract
- Letter of support submitted by the thesis advisor

Deadline: All application materials must be received by AUGUST 20th, 2014.

Invited speakers:

The following invited speakers confirmed their attendance:

  • D. Buca (Research Center Jülich, D), SiGeSn for optoelectronics
  • M. Heuken (Aixtron, D), IIIV MOCVD for CMOS
  • Y.-H. Xie (UCLA, USA), Graphene - plasmonic interaction
  • R. Erni (EMPA, CH), Advanced HRTEM techniques
  • S. Spiga (MDM-CNR, I), RRAM novel materials
  • A. Marzegalli (University of Milano, I), Ge Heteroepitaxy
  • M. Onomura (Toshiba, JPN), Nitrides
  • P. Storck (Siltronic, DE), virtual SiGe substrates
  • G. Chahine (ESRF, FR), Advanced Material Characterization using Nano and Micro diffraction Techniques
  • D. Petersen (Capres, DK), Micro-Hall on ultra-narrow device structure
  • V. Sverdlov (TU Vienna, AUT), Spin behaviour in strained films
  • P. Davids (Sandia Nlabs, USA), CMOS Si photonics for exascale computing
  • C. Ahn (Yale University, USA), Oxides for photonics
  • R. Czajka (TU Poznan, POL), STM on contacts for Ge
  • S. Takagi (University of Tokyo, JPN), fabrication of IIIV on Si via wafer bonding
  • S. Joly (CEA-LETI, FR), Optical sensors for health monitoring
  • T. Pensala (VTT Technical Research Centre of Finland), Piezomaterials for BAW/SAW filters

Scientific committee:

  • Czeslaw Skierbiszewski (Polish Academy of Sciences, Warsaw; Poland)
  • Francesco Montalenti (Università Milano Bicocca; Italy)
  • Philippe Boucaud (IEF- Universitè Paris Sud, France)
  • Leo Miglio (L-NESS, Universita' di Milano Bicocca and Politecnico di Milano, Italy)
  • Catherine Dubourdieu (CNRS, Institut des Nanotechnologies de Lyon, France)
  • Jean-Michel Hartmann (LETI, France)
  • Dieder Landru (SOITEC, France)
  • Kerstin Volz (Philipps-Universität Marburg Germany)
  • Inga Fischer (IHT, Stuttgart)
  • Dmitri Lubyshev (IQE PA, USA)
Start atSubject View AllNum.
09:45
Authors : W. M. Klesse1, G. Capellini2;3, M. Y. Simmons1;4 and G. Scappucci1
Affiliations : 1 School of Physics, University of New South Wales, Sydney, NSW 2052, Australia; 2 IHP, 15236 Frankfurt (Oder), Germany; 3 Scienze, Università Roma Tre, 00146 Roma, Italy; 4 ARC-CQC2T, University of New South Wales, Sydney, NSW 2052, Australia

Resume : For the fabrication of Germanium (Ge)-based high performance nanoelectronic and photonic devices alternative in-situ doping strategies allow precisely controlled n-type doping with high dopant activation while avoiding ion-implantation induced damage of the crystal. Here, we shall discuss in-situ Phosphorus (P)-δ-doping in ultra-high vacuum and directly compare the dopant precursors phosphine (PH3) gas and P2 molecules. Using STM we studied at the atomic level the underlying surface chemistry of PH3 and P2 molecules on Ge(001), allowing us to determine the P incorporation temperature into Ge for both doping precursors to ~200 ºC. Next, we observed that saturation dosing from P2 yields a nearly full monolayer (1 ML) P surface coverage by directly identifying P-P dimers terminating the Ge(001) surface. Dosing with PH3, however, appears limited to a maximal surface coverage of 0.5 ML, suggesting that PH3 desorption (~250ºC) prevents the formation of P-P dimers on the Ge(001) surface. Finally, we adapt this doping technique to Ge-on-Insulator films whilst preserving the structural integrity and strain levels of the substrate. By carefully optimizing the doping parameters we optimize the electrical properties of thin Ge:P films to achieve ultra-sharp dopant profiles and high active electron densities (>1x1020 cm-3). Our results bode well towards both the realization of ultra-shallow source/drain contacts in Ge-based transistors and the development of an efficient Ge-on-Si laser.

J.1.3
10:00
Authors : F. Oliveira (1), I. A. Fischer (1) , S. Stefanov (2), S. Chiussi (2) , M. Cerqueira (3), M. Vasilevskiy (3), J. Schulze (1)
Affiliations : (1) Institut für Halbleitertechnik, Universität Stuttgart, 70569 Stuttgart, Germany; (2) Dpto. Fisica Aplicada, Univ. de Vigo, Campus Universitario Lagoas Marcosende, Vigo, Spain; (3) Centre of Physics University of Minho, University of Minho, Campus de Gualtar, and International Iberian Nanotechnology Laboratory, Braga, Portugal;

Resume : We report on the fabrication and structural characterization of epitaxially grown ultra-thin layers of Sn on Ge virtual substrates. Samples with 1 to 5 mono-layers (ML) of Sn on Ge virtual substrates were grown using solid source molecular beam epitaxy (MBE) and characterized by atomic force microscopy (AFM). We determined the critical thickness at which the transition from two-dimensional to three-dimensional growth can be observed as a result of the large lattice mismatch between Ge and Sn (~ 15 %). By depositing Ge on top of Sn layers, which have thicknesses at or just below the critical thickness, we were able to fabricate ultra-narrow GeSn multi-quantum-well structures with high Sn content that are fully embedded in Ge. We present experimental results on samples with ten GeSn wells separated by 5, 10 and 15 nm thick Ge spacer layers that were characterized by High Resolution Transmission Electron Microscopy (HR-TEM), Energy Dispersive Spectroscopy (EDS) and Selected Area Diffraction (SAD). We discuss the structure and intermixing observed in the samples.

J.1.4
11:45
Authors : O. Supplie [1,2], S. Brückner [1,2], P. Kleinschmidt [1,2], O. Romanyuk [3], H. Döscher [1], MM. May [2], C. Höhn [2], F. Große [4], and T. Hannappel [1,2]
Affiliations : [1] TU Ilmenau, Institut für Physik, FG Photovoltaik, Ilmenau, Germany, [2] Helmholtz-Zentrum Berlin, Institute for Solar Fuels, Berlin, Germany, [3] Academy of Sciences of the Czech Republic, Institute of Physics, Prague, Czech Republic, [4] Paul Drude Institut für Festkörperelektronik, Berlin, Germany

Resume : Detailed understanding of Si preparation and formation of polar-on-nonpolar interfaces is a prerequisite for heteroepitaxial integration of III-V semiconductors on Si. By varying preparation conditions in metalorganic vapor phase epitaxy (MOVPE) ambient, we can choose between energetically and kinetically driven Si(100) step formation, which results in majority domains of monohydride-terminated Si dimers oriented either parallel or perpendicular to the step edges [1]. The sublattice orientation of subsequently grown single-domain heteroepitaxial GaP films depends on the domain type of the Si substrate surface. In an abrupt interface model, the correlation of the orientation of P dimers and Si dimers, respectively, by in situ reflection anisotropy spectroscopy (RAS) favors Si-P bonds at the heterointerface which contradicts literature [2]. Also ab initio density functional theory (DFT) calculations show that Si-P bonds are energetically favored over Si-Ga bonds for P-rich growth conditions at abrupt interfaces. In thermodynamic equilibrium, the energetically most favorable interface is compensated with an intermixed interfacial layer. In situ RAS, however, reveals that the GaP sublattice orientation depends on the P chemical potential during nucleation which agrees with a kinetically limited formation of abrupt interfaces. [1] S. Brückner et al., PRB 86:195310 (2012); New J. Phys. 15:113049 (2013). [2] Beyer et al. JAP 111:083534 (2012).

J.2.3
12:15
Authors : T. Baron1, R. Cipro1, M. Martin1, F. Bassani1, S. Arnaud1, S. David1, V. Gorbenko1, 2, JP. Barnes2, Y. Bogumilovicz2, P. Gergaud2, N. Rochas2, V. Loup2, C. Vizioz2, K. Yckache2, N. Chauvin3, X.Y. Bao4, Z .Ye4, D. Carlson4, JB Pin4, E. Sanchez4
Affiliations : 1Univ. Grenoble Alpes, LTM, F-38000Grenoble, France CNRS, LTM, F-38000Grenoble, France 2Univ. Grenoble Alpes, F-38000 Grenoble, France, CEA-LETI, MINATEC Campus, F-38054 Grenoble, France 3Institut des Nanotechnologies de Lyon (INL)-UMR5270-CNRS, INSA-Lyon, Universit? de Lyon,7 Avenue Jean Capelle, 69621 Villeurbanne, France 4Applied Materials, 3050 Bowers Avenue, Santa Clara, CA 95054, USA

Resume : Replacing silicon with high-mobility channel materials such as InGaAs will be surely the next evolution of MOSFET devices. Alternative materials such as High- dielectrics and metal gates have already been successfully introduced. InGaAs based channels hold the promise of circuits operating at lower Vdd and hence consuming low power as the dynamic power roughly scales as V2dd. Two different strategies for integrating As based compounds as MOSFET channels are actually foreseen: fully depleted III-V/On Insulator or FinFET. This integration still faces many challenges like direct III-V epitaxy on Si, channel/high k interface control, and contact resistance. We focus on the direct growth of As compounds on Si(100) 300 mm substrates. GaAs and InGaAs layers are grown by an Applied Materials MOCVD tool. TMIn, TMGa and TMAl are used as group III elemental precursors whereas TBAs is used as group V elemental precursor. Typical growth temperature ranges between 300 and 700?C and pressure ranges between 1 and several hundred Torrs. We have studied the structural and the physical properties of GaAs, InGaAs, AlGaAs layers grown either on blanket or patterned Si(100) wafers by FIBSTEM, TEM, SIMS, ?PL, cathodoluminescence. We showed an improvement of the material quality as they are elaborated in SiO2 cavity even with an aspect ratio less than 2. Antiphase boundary and dislocation densities are strongly decreased as the width of the cavity goes bellow 100 nm. By adjusting properly the growth conditions and the stack in the quantum well structure, we were able to observe room temperature micro-photoluminescence of single InGaAs QW, with In composition ranging between 10 and 40%.

J.2.5
14:30
Authors : Rémi Comyn, Yvon Cordier, Vincent Aimez, Hassan Maher
Affiliations : Laboratoire Nanotechnologies Nanosystèmes (LN2)- CNRS UMI-3463, Université de Sherbrooke, 3000 Boulevard Université, Sherbrooke, J1K OA5, Québec, Canada; CRHEA-CNRS, Rue Bernard Gregory, Valbonne, 06560, France;

Resume : A successful monolithic integration of silicon CMOS with GaN-HEMTs by epitaxy requires the preservation of both kinds of device performances during the process. In the CMOS-first scenario, GaN is grown in defined areas of the Si substrate (Selective Area Growth, SAG), while existing CMOS areas are protected by a dielectric stack. However, the thermal budget of GaN growth is expected to strongly impact the CMOS characteristics. More, the thermal cycles involved in the epitaxy generate a severe stress on the protective dielectric layers above the CMOS, leading to a risk of delamination and CMOS devices damaging. It is therefore necessary to investigate in which extend the growth thermal budget could be reduced without penalty on the performances of GaN-HEMTs. In the present study, different structures were grown on Si by ammonia-MBE with standard and reduced thermal budgets, and then compared with regard to structural and electrical properties (AFM, SEM, XRD, C-V, Hall effect, and GaN transistors output characteristics). The study sets the limit for a trade-off between CMOS and GaN-HEMTs degradation. Based on these results, GaN SAG has been developed with a lower thermal budget (Tmax reduced from 920°C to 850°C). For this, a dielectric stack was designed in order to achieve the protection of the buried CMOS devices during the growth. The elaboration of low thermal budget GaN SAG brings us a step forward on the way to the monolithic integration of GaN-HEMTs with silicon CMOS.

J.3.2
15:15
Authors : M. Scigaj [1,2], N. Dix [1], I. Fina [1], R. Bachelet [1], V. Skumryev [2], G. Herranz [1], J. Fontcuberta [1], F. Sánchez [1]
Affiliations : [1] Institut de Ciència de Materials de Barcelona (ICMAB-CSIC), Campus de la UAB, Bellaterra 08193, Spain; [2] Dep. de Física, Universitat Autònoma de Barcelona, Campus de la UAB, Bellaterra 08193, Spain

Resume : Multiferroic materials are appealing for its application in microelectronic devices, but coexistence of ferroelectricity and ferromagnetism in a single material is generally restricted to low temperatures. Artificial multiferroics, combining ferroelectric (FE) and ferromagnetic (FM) phases are an alternative. High quality multiferroic FM/FE heterostructures can be fabricated on oxide single crystals, but its integration with silicon is elusive. We show here that high quality epitaxial CoFe2O4/BaTiO3 bilayer can be grown on buffered Si(001) by pulsed laser deposition. The use of a complex LaNiO3/CeO2/YSZ buffer layer is key to obtain epitaxy of BaTiO3 and CoFe2O4, and favour c-axis orientation of BaTiO3. Consequently, CoFe2O4/BaTiO3/LaNiO3/CeO2/YSZ heterostructures were deposited on Si(001) in a single process by pulsed laser deposition assisted with high energy electron diffraction (RHEED). Atomic force microscopy, X-ray diffractometry, and RHEED confirm high structural quality of the CoFe2O4/BaTiO3 heterostructures. CoFe2O4/BaTiO3 bilayers display good multiferroic properties, with high values of magnetization (> 200 emu/cm3) and polarization (>15 uC/cm2) at room temperature. Remarkably, the polarization of CFO/BTO bilayers is enhanced compared with bare BTO films and there are no fatigue up to more than 3xE9 cycles. Finally we show the influence of the CoFe2O4 on the ferroelectric polarization and current leakage of the BaTiO3 films.

J.3.5
17:30
Authors : J. Laube, S. Gutsch, D. Hiller, M. Zacharias
Affiliations : Laboratory for Nanotechnology, Department of Microsystems Engineering - IMTEK, University of Freiburg, Georges-Koehler-Allee 103, 79110 Freiburg im Breisgau, Germany

Resume : Silicon based light emitting devices (LEDs) could enable fast, efficient, and power saving on-chip communication. Since bulk-Si (indirect band gap) is not suitable for any type of LED, Si nanocrystal (Si NC) based LEDs were proposed [1,2] due to their quasi direct gap and 5 orders of magnitude higher luminescence quantum yields. In order to fabricate a surface emitting Si NC device a transparent conductive oxide (TCO) deposition process without radiation or impact damage is mandatory to prevent deterioration of the quantum dots. We present Si NC LEDs fabricated by conventional sputtering of indium tin oxide (ITO) [3] and identify the damage caused by the sputtering-inherent and inevitable impact of accelerated heavy ions. For comparison we present a fabrication route based on low-impact thermal atomic layer deposition (ALD) of zinc oxide (ZnO). Zinc oxide is usually a n-type semiconductor based on hydrogen based defects and oxygen defects [4,5]. We show that the long term stability of the conductivity is limited which we attribute to the effusion of hydrogen even at ambient conditions. Therefore, we evaluate a method to encapsulate the hydrogen in the ZnO by an in-situ deposited ALD aluminum oxide (Al2O3) diffusion barrier. [1] K.Y. Cheng, et al., Nano Lett. 11, 1952 (2011) [2] R.J. Walters et al., Nature Mater. 4, 143 (2005) [3] J. Lopez-Vidrier et al., JAP 114, 163701 (2013) [4] Janotti et al., Nat mater 6, 2007 [5] Kim et al., Solid State Commun 152, 2012

J.J.11
17:30
Authors : L. Rebohle, R. Wutzler, S. Prucnal, M. Helm, W. Skorupa
Affiliations : Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum Dresden - Rossendorf, Bautzner Landstraße 400, 01328 Dresden, Germany

Resume : InAs, InGaAs and GaAs nanocrystals (NCs) were fabricated by sequential ion implantation and flash lamp annealing. In detail, silicon-on-insulator (SOI) structures were provided with a SiO2 capping layer followed by the sequential implantation of In, Ga and As ions with fluences in the range of a few 1016 at./cm2. In order to get NCs at defined positions, in some cases ion implantation was performed through an additional, patterned Al capping layer. In the following step of flash lamp annealing the NCs will be formed in the Si device layer of the SOI wafer by liquid phase epitaxy. The resulting NCs are mostly single-crystalline with sizes of a few tens of nm. Transmission electron microscopy (TEM), Raman spectroscopy, atomic force microscopy (AFM), Rutherford Backscattering (RBS) and optical characterization are used to investigate the microstructure and the formation process of the NCs.

J.J.13
17:30
Authors : V. S. Senthil Srinivasan, I. A. Fischer, A. Hornung, J. Schulze
Affiliations : Institute for Semiconductor Engineering, University of Stuttgart, Pffafenwaldring 47, 70569 Stuttgart, Germany

Resume : Ge1-xSnx is a material of interest for high performance logic and optoelectronic applications because of its high mobility and the fact that a direct band gap is predicted in the unstrained material for x exceeding ~ 0.1. Ge1-xSnx channel transistors have been investigated for CMOS applications. Metal/n-Ge contacts usually exhibit large specific contact resistivities as a result of Fermi level pinning at the interface, which in the case of MOSFETs degrades the device on-currents. This motivated us to investigate interface properties of metal/Ge1-xSnx contacts with respect to Sn percentage and metal work function. The Ge1-xSnx films with different Sn concentration were grown by molecular beam epitaxy (MBE). Transmission-line-measurement (TLM) structures and Schottky diodes were fabricated by structuring a mesa using reactive ion etching (RIE) followed by passivation with low temperature SiO2, structuring of contact holes and deposition of the respective metals. Schottky barrier heights and contact resistivities of Metal/Ge1-xSnx structure with different metal work functions and Sn concentrations were extracted from current ? voltage measurements and discussed.

J.J.20
17:30
Authors : T. Bentrcia1, F. Djeffal2, Z. Dibi2 and D. Arar2
Affiliations : 1Physics Department, University of Batna, Batna 05000, Algeria Email: toufikmit@yahoo.com 2Electronics Department, University of Batna, Batna 05000, Algeria Email: faycal.djeffal@univ-batna.dz, faycaldzdz@hotmail.com

Resume : The use of a lower band-gap material in the channel region of the MOSFET, such as SiGe, is a potential candidate given their compatibility with the process developed for pure Si-based devices. In addition, an increasing in the drain current and the transconductance due to the increased electrons mobility in SiGe material is expected. However, Bang gap narrowing due to Ge mole fraction increasing channel is critical problem that leads to electrical performance degradation. Therefore, in this paper we present a novel graded doping channel-based approach to improve the device reliability. Based on 2-D numerical investigation of a nanoscale SiGe Double Gate MOSFET including the defects in the interface region, in the present paper a numerical models for subthreshold characteristics by including the interfacial defects, after considering the uniform function approximation for the interface defects distribution at the drain said, are developed to explain the impact of the graded doping profile on the immunity behavior of the nanoscale transistor against the defect densities. In this context, subthreshold characteristics of the proposed design are analyzed by 2-D numerical simulation and compared with conventional uniform doping profile DG MOSFET characteristics.

J.J.21
17:30
Authors : A.Dolgyi1, E.Chubenko1, H.Bandarenka1, A.Klyshko1, M.Balucani2, V.Bondarenko1
Affiliations : 1 Belarusian State University of Informatics and Radioelectronics 2 University of Rome "Sapienza"

Resume : A fabrication technique of metallic (Me) layers with a thickness of 2-15 microns which are strongly or weakly bound with a silicon (Si) wafer for Layer Transfer was developed. A managing adhesion of the Me layers was carried out by pre-formation of a copper/porous silicon (Cu/PS) sub- layer on the Si wafer. The Cu/PS layers were formed by anodizing the Si wafer and further Cu immersion deposition from a Cu sulfate and HF water solution. Than an electrochemical deposition was used to form Me layers. It was found that the Me layer transfer can go in 2 ways, depending on a PS porosity (p): (1) p<30% or p>85% - a separation of the Me layer occurs along its interface with PS; 30%85% Si crystallites of PS have an increased chemical resistance due to small sizes (<7 nm) and Cu ions from the immersion solution are unable to oxidize them and deposit in the pores. In the second case, an adhesion of the Me layers can be highly controlled in the range of 1.2-4.5 MPa by porosity variation. It should be noted that the Me layers which were deposited on a Cu-free PS showed a poor adhesion manageability. The developed technique is shown to be promising for the fabrication of interconnections between different wafers for MEMS (Probe Cards, Power Modules, etc).

J.J.29
17:30
Authors : A. Novikau, O. Nalivajko*, S. Prakopyeu, A. Chizh, P. Gaiduk
Affiliations : Belarusian State University, 4 Nezavisimosti av., Minsk, Belarus; *JSC “INTEGRAL”, Kazintsa sq.1, Minsk, Belarus

Resume : The main challenge for Ge and SiGe layers integration into the low-cost near-infrared silicon based photodetectors is high absorption coefficient, long carriers lifetime and others. In the present work we studied the formation of multilayer struc-tures based on polycrystalline SiGe and Ge films, deposited at reduced pressure on silicon substrates. The low pressure hot wall horizontal reactor "Lada- 34" was used for the de-position of Ge, SiGe and a-Si cap layers at 500° C. The 0.5 and 1.0 um thick Ge films were used as the reference samples. Hydrogen high temperature processing was per-formed at 850°C using the epitaxial silicon chamber «Gemini-1". The structural properties of LPCVD grown thin Ge and SiGe films treated at hydrogen atmosphere has been investigated using Rutherford backscattering and scanning electronic microscopy methods. RBS and SEM analysis allowed to establish the structural properties and morpho-logical transformations is the Ge based structures. It is found that annealing in hydrogen enhances the mobility and diffusion of germanium atoms. This effect can be used to re-duce surface roughness of the structures using an optimized process regime. It is shown that maximum absorption at 1,3 µm wavelength is demonstrated for heterostructures based on Ge layers of 1.0 µm thick or higher.

J.J.32
17:30
Authors : M. H. Zoellner1, G. Niu1, P. Zaumseil1, J.-H- Jhang2, A. Schaefer2, M. Bäumer2, H. Wilkens3, J. Wollschläger3, F. Boscherini4, F. dAcapito5, T. Schroeder1,6
Affiliations : 1 IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany 2 Universität Bremen, Institut für angewandte und physikalische Chemie, Leobener Str. 2, 28357, Germany 3 Universität Osnabrück, Fachbereich Physik, Barbarastr. 7, 49076 Osnabrück, Germany 4 University of Bologna, Department of Physics and Astronomy, viale C. BertiPichat 6/2, 40127 Bologna, Italy 5 Consiglio Nazionaledelle Ricerche, Instituto Officinadei Materiali, Operative Group in Grenoble, c/o European Synchrotron Radiation Facility, BP 220, 38043 Grenoble Cedex, France 6 Brandenburgisch Technische Universität, Institute of Physics , Germany, 03046 Cottbus

Resume : Ceria (CeO2) attracted tremendous attention for diverse applications, such as catalysis, solid oxide fuel cells, and gas sensing, thanks to its high oxygen mobility as well as storage capacity. The origin of these promising abilities can be traced back to the presence of oxygen vacancies, causing a change in the crystallographic and electronic structure (Ce4+/Ce3+). Its neighboring rare earth oxide, praseodymia, shows opposite redox properties in terms of Pr valence state exchange (Pr4+/Pr3+) allowing to tailor the redox properties of mixed CePr oxide compounds. Thus, additional oxygen vacancies in Pr-doped CeO2 are created by a Pr4+/Pr3+ valence change in the CeO2 matrix, probably resulting in a strong local lattice distortion. Here, oxygen vacancy formation in single crystalline epitaxial Ce1-xPrxO2-δ (x = 0-1) thin films on Si(111) is studied by Raman spectroscopy in dependence on the Pr-concentration and temperature. The correlated global and local structure distortion was investigated by laboratory and synchrotron based X-ray diffraction (XRD) and extended X-ray absorption fine-structure (EXAFS) measurements, respectively. Furthermore, the valence states of Ce and Pr were explored by X-ray photoelectron spectroscopy (XPS). Concluding, it is found that we are able to tune oxygen vacancy concentration, oxygen storage capacity and oxidative capability by mixing Pr cations into the CeO2 fluorite lattice and identify the atomistic origin of these tailored redox properties.

J.J.39
Start atSubject View AllNum.
14:45
Authors : Anna Giorgioni, Elisa Vitiello, Emanuele Grilli, Emiliano Bonera, Mario Guzzi, Fabio Pezzoli
Affiliations : LNESS and Dipartimento di Scienza dei Materiali, Università degli Studi di Milano Bicocca, via Cozzi 55, I-20125 Milano, Italy

Resume : The polarization of the photoluminescence (PL) from the indirect gap of bulk Ge is studied after optical orientation by absorption of circularly polarized light through the direct gap. The spin relaxation time ts is then estimated by combining the polarization degree and the decay time of the indirect gap emission. Ge is a promising material for spin-optoelectronics due to its feasible integration on Si, its noticeable spin properties and the possibility of achieving room temperature lasing action. In order to merge the spin degree of freedom and the photonics functionalities, the knowledge of properties such as the electron spin lifetime is of practical and fundamental importance. In this work we address this issue reporting the first evidence that low temperature PL from the indirect gap of bulk Ge is circularly polarized. This is the smoking gun proof that spin-polarized electrons preserve their orientation during the long dwell time in the L valley. We experimentally verified the selection rules for phonon mediated transitions showing an excellent agreement with the theory. Finally, to estimate ts we applied time-resolved PL, yielding in addition accurate data for the carrier lifetime. Hundreds of ns long ts is found providing the longest estimation reported at T<30K. Our results demonstrate the prominent and viable role of Ge for merging photonics and spintronics on the same materials platform.

J.8.3
15:00
Authors : V. S. Senthil Srinivasan, I.A. Fischer, R. Koerner, E. Rolseth, J. Schulze
Affiliations : Institute for Semiconductor Engineering, University of Stuttgart, Pffafenwaldring 47, 70569 Stuttgart, Germany

Resume : CMOS compatible high mobility channel device on Si platform is a promising approach for future VLSI technology nodes. However mobility degradation caused by the impurity scattering is a major concern to achieve high performance logic devices with conventional channel. Delta doped channel device could be an option for mobility enhancement where the dopant is confined to a single plane of crystal. Thus the delta doped channel devices offer high mobility than the homogeneously doped channel devices by reducing the impurity scattering. We propose a delta doped channel Field Effect Transistor (delta doped FET) with high mobility Germanium (Ge) as a channel material. In this work we have fabricated P-channel delta doped Ge FET with different channel lengths (75, 50, 25, 10 nm). Blanket epitaxial device layers were grown by molecular beam epitaxy (MBE) and a low temperature (< 400 °C) CMOS process flow was followed to fabricate mesa, passivation oxide deposition, contact hole formation and contact metallization. Devices with different mesa areas were produced and characterized. Further, we replaced the Ge P-delta layer with GeSn P-delta layer in the channel and analyzed their performance.

J.8.4
16:30
Authors : Didier Landru, Oleg Kononchuk, Pablo Acosta, Nicolas Daval, Christophe Gourdel.
Affiliations : SOITEC, Parc technologique des Fontaines, F-38190 Bernin, FRANCE

Resume : Fully Depleted (FD) devices provide the electrostatic boost that is required to manufacture CMOS technology with gate lengths smaller than 25 nm. 3D Multi Gate and planar FD SOI are currently developed by the industry. Both demonstrate great DIBL at extremely scaled gate lengths that translate into superior performance at reduced Vdd. SOI substrates will play a key role for these new technologies. They greatly simplify the 3D FET process and reduce device variability. Planar Fully-Depleted technology has already been demonstrated on SOI wafers with very high energy efficiency, and is entering production at the 28 nm node. SOI substrates for FD devices require a few tenths of nanometers thin silicon film over a buried oxide layer. The uniformity of the SOI top silicon layer is critical because the SOI thickness is directly related to the transistor VT value, and this, from the transistor scale to the full wafer scale. This lead to extremely tight thickness specifications of 1 nm of SOI thickness range over a 300 mm substrate. In this presentation, we review the technical challenges to create SOI substrates for FD applications. First we consider the metrology technologies needed to get a viable multi-scale thickness characterization. Then, we compare the various methods to manufacture SOI substrates in terms of final thickness control. Finally, we give examples of state-of-the-art SOI substrates and question about the future limitations in terms of SOI thickness control.

J.9.2
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Materials Science - Advanced characterization (Joint with symposia H & N) : Wojciech Paszkowicz, Thilo Glatzel, and Jean Fompeyrine
14:00
Authors : T. Dane 1, E. Di Cola 1, L. Lardiere 1, C. Montero 2, C. Riekel 1, M. Sztucki 1, B. Weinhausen 1, and M. Burghammer 1,3
Affiliations : 1 European Synchrotron Radiation Facility, Grenoble, France; 2 Université Montpellier 2, Laboratoire de Mécanique et Génie Civil , Montpellier, France; 3 Ghent University, Department of Analytical Chemistry, Ghent, Belgium

Resume : At third generation synchrotrons focused X-ray beams have been used for about two decades adding spatial resolution to diffraction experiments. Whilst the early days the typical beam size was at the 10 micron scale, today nano-beams ranging from few tens of nanometers to a few hundred nanometers are available to investigate micro-/nano-crystal arrangments. We will discuss instrumental aspects of nano-beam scanning diffraction, exemplified on the ID13 nano-probe. This comprises the production of nano-beams, requirements of positional stability, the selection of different types of area detectors, the layout of the nano-goniometer, and sample manipulation. Many scientific topics that can in principle be addressed with nano-diffraction can be enhanced by the use of complementary methods or sample environments in order to perform the experiment under in-situ/in-operando conditions such as working at elevated temperatures [1] and mechanical deformation. Examples from a wide range of scientific applications from material science to polymer research will be presented in the second part of this contribution. Nano-diffraction can be used, for instance, to investigate texture, strain, particle size, and phase composition of thin films and other materials. Mapping the orientation of its crystalline component, the longitudinal morphology of high performance polymer fibres can be imaged in detail at the 100 nm scale. We will conclude with an outlook on future opportunities of nano-diffraction in view of the availability of high performance pixel array detectors and substantial upgrades foreseen of the 3rd generation synchrotrons at the ESRF and elsewhere. [1] Rosenthal, M., et al (2014) J. Synchrotron Radiat. 21 223-228

J.HJN.1
16:30
Authors : Thomas Dittrich
Affiliations : Helmholtz Center Berlin for Materials and Energy, Hahn-Meitner-Platz 1, 14109 Berlin, Germany

Resume : Investigation of photovoltaic and photo-catalytic materials by surface photovoltage techniques Abstract: Charge separation in space is crucial for the application of photovoltaic and photo-catalytic materials. Surface photovoltage (SPV) measurements in the Kelvin-probe and fixed capacitor arrangements give information about spectral, time and temperature dependent charge separation in space in semiconducting materials and in ultra-thin charge-selective layers or layer systems. SPV signals contain information about mechanisms of charge separation, electronic transitions from which charge separation is possible, charge transport and recombination. Advantages of SPV techniques are (i) the local sensitivity in one dimension related to regions of charge separation, (ii) the high sensitivity up to charge separation in molecular monolayers, (iii) the ability to bridge the pressure gap between ultra-high vacuum, gas atmospheres and electrolytes and (iv) the special access to materials specific properties. The complex dependence of SPV signals on photo-generation, carrier dynamics and photo-chemical processes makes a straight forward interpretation of SPV signals often difficult so that the investigation of model systems is required. A brief introduction into SPV techniques will be given. Examples of mechanisms of charge separation will be demonstrated for the characterization of charge separation in surface treated semiconductors and across organic and quantum dot monolayers and nano-composites.

J.HJN.5
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09:15
Authors : Inga A. Fischer (1), Torsten Wendav (2), Lion Augel (1), Songchai Jitpakdeebodin (1), Filipe Oliveira (1), Kurt Busch (2), Jörg Schulze (1)
Affiliations : (1) Institut für Halbleitertechnik (IHT), Universität Stuttgart, Pfaffenwaldring 47, Stuttgart, 70569, Germany; (2) Humboldt-Universität zu Berlin, Institut für Physik, AG Theoretische Optik & Photonik, 12489 Berlin, Germany;

Resume : Electro-optical devices with multi-quantum-well (MQW) structures based on the ternary alloy SiGeSn in their active region have been proposed as a means to realize laser diodes as well as modulators. Here, we report on the fabrication and electrooptical characterization of Si0.38Ge0.61Sn0.01/Si0.20Ge0.65Sn0.15 MQW PIN diodes. The composition of both the barrier and the well regions is chosen in such a way that the quantum well structures can be fabricated strain-balanced on Ge. The SiGeSn layers were grown with solid source molecular beam epitaxy on Si (100) substrates using a Ge virtual substrate to accommodate the lattice difference. Fluxes of the Sn and Ge effusion cells as well as the Si electron beam evaporator were calibrated separately and adjusted to obtain the desired alloy structures with a total growth rate of 1 Å/s. The SiGeSn MQW active region was deposited at a substrate temperature of 160 °C to avoid Sn segregation. Two PIN diodes, in which two and four quantum wells with well and barrier thicknesses of 10 nm each are sandwiched between B- and Sb-doped Ge-regions, were fabricated as single-mesa devices using a low-temperature fabrication process. We discuss measurements of the diode characteristics, the optical responsivity and electroluminescence at room temperature and compare the results with theoretical predictions from bandstructure calculations.

J.12.3
 
Materials Science - Advanced Characterization : Peter Storck
14:00
Authors : G. Chahine1, M.I. Richard12, T. Schroeder3, G. Capellini3, TN Tran Thi1, T. U. Schülli1
Affiliations : 1 European Synchrotron Radiation Facility, BP 220, F-38043, cedex, Grenoble, France; 2 Aix-Marseille Université, CNRS, IM2NP UMR 7334, 13397 Marseille Cedex 20, France; 3 Innovations for High Performance Microelectronic, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany

Resume : The physical properties of nano-materials and microelectronic device performances can be manipulated and improved by strain engineering processes. Induced lattice distortions as strain or bending can now be characterized by high-resolution x-ray diffraction imaging techniques. Among these tools, the scanning x-ray diffraction microscopy (SXDM) is becoming a routine tool for structural characterization of nanostructures. In this context, a scanning probe technique together with a new software package have been optimized and implemented at the ID01 beamline (ESRF, Grenoble). The technique consists in a two-dimensional (2D) quicK continuous Mapping (K-Map) with sub micrometer resolution of a sample at a given reciprocal space position. These real space maps are recorded in continuous motion of the sample for every point across a rocking curve while recording 2D detector images using a sufficiently fast pixel detector. Five dimensional data sets are then produced consisting of millions of detector images. The images are processed by a user friendly X-ray Strain and Orientation Calculation Software (XSOCS) which has been developed at ID01 for automatic and fast analysis. It separates tilt and strain, and generates 2D maps of these parameters. At spatial resolutions of typically 200 to 800 nm, this quick imaging technique obtains strain sensitivity below ∆a/a=10-5 and a resolution of tilt variations down to 10-3 ° over a field of view of 200 x200 µm2. In this talk, I will present the K-Map technique and the XSOCS software. In addition, I will show some examples: (i) The ESRF logo, printed in a SiGe thin layer, for testing the K-Map technique as well as XSOCS. (ii) The investigation of strain distribution of Ge microstripes, a candidate as active material for integrated light emitter applications.

J.14.1
15:00
Authors : R. Czajka
Affiliations : Institute of Physics, Faculty of Technical Physics, Poznan University of Technology, Nieszawska 13 A, 60-965 Poznan, Poland

Resume : Distinct reactivity of the Si(001) surface makes the integration of the hybrid systems difficult what cancels advantages of the Si(001) in such systems. Estimation of the possibility to replace the inalienable Si(001) substrate (which is necessary in the classical semiconductor-oxide-metal systems) with the hybrid Si(111)/ Ge(111) substrates is one of the intermediate goals of researchers working in nanoelectronics. The final aim is the elaboration of the strategy leading to control functionalization of Si(111), Ge(111) and Ge(001) surfaces as high yield substrates for hybrid (organic/inorganic) molecular nanoelectronics. Using pre-modified Si(111) and Ge(111) substrates (instead of Si(001) one) by adsorption of chosen metals, e.g. Ni on Si and Ba on Ge, could be the first step within this strategy. Obtained periodic structure of the modified substrates and theirs electronic properties were characterized by scanning tunneling microscopy and spectroscopy (STM/S) methods. This work was in part supported by the NSC Project N N202 195840 and by The Polish Ministry of Science and Higher Education (Statutory activity) within the Project no 06/62/DSPB/214/2014.

J.14.4
16:30
Authors : M. H. Zoellner1, G. Chahine2, M.-I. Richard2,3, P. Zaumseil1, G. Capellini1, C. Reich1, P. Storck4, T. U. Schulli2, T. Schroeder1,5
Affiliations : 1 IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany 2 European Synchrotron Radiation Facility, BP 220, 38043 Grenoble Cedex, France 3 Aix-Marseille Universit?, CNRS, IM2NP UMR 7334, 13397 Marseille Cedex 20, France 4 Siltronic AG, Hans-Seidel-Platz 4, 81737 M?nchen, Germany 5Brandenburgisch Technische Universit?t, Institute of Physics , Germany, 03046 Cottbus

Resume : SiGe "virtual substrates" are promising for integrating strained Si, Ge and III/V semiconductors as closed films on a Si(001) platform. Such semiconductor films are of interest in advanced CMOS technology. Although, growth and relaxation processes of SiGe buffer layers on Si(001) are well investigated and major achievements were made, control over the structural homogeneity of SiGe buffers below micro-meter scale is still a challenge for global integration on 300 mm Si(001) wafers. The recently developed synchrotron-based Scanning X-ray Diffraction Microscopy (SXDM) at the beam line ID01 of the European Synchrotron radiation facility (ESRF) is ideally suited to non-destructively image local tilt, strain and composition variation with sub-micron resolution of heteroepitaxial systems [1] and was thus applied to polished and unpolished step graded Si0.3Ge0.7/Si(001) buffers. Within a scan range of 90 μm x 90 μm with 750 nm step size at each real space position (x, y) a 3D (qx, qy, qz) reciprocal space map around the (004) and (113) Bragg reflection is monitored. The local lattice constant and orientation were extracted by the Strain Orientation Calculation Software. Qualitatively, it was found that SXDM is able to image by lattice tilt studies the cross-hatch pattern. The capability of the technique to determine lattice parameters in a quantitative way demonstrates the high quality of the SiGe/Si(001) systems. [1] G. A. Chahine et al., J. Appl. Cryst. 47, 762 (2014).

J.15.2
16:45
Authors : N. von den Driesch1, S. Wirths1, D. Stange1, A.T. Tiedemann1, G. Mussler1, T. Stoica1, S. Lenk1, U. Breuer2, D. Gruetzmacher1, S. Mantl1, D. Buca1
Affiliations : 1: Peter Gruenberg Institute (PGI 9) and JARA-Fundamentals of Future Information Technologies, Forschungszentrum Juelich, 52425, Germany; 2: Central Division of Analytical Chemistry (ZCH), Forschungszentrum Juelich, 52425, Germany

Resume : Germanium Tin (GeSn) is a promising material for Group IV photonics due to the transition to a fundamental direct bandgap semiconductor of cubic GeSn with Sn concentrations above 8 at.%. Despite the successful growth of high quality pseudomorphic GeSn alloys, the realization of strain relaxed layers is still challenging. We will report on the reduced-pressure CVD epitaxial growth of GeSn layers with Sn contents from 5 to 14 at.% and thicknesses between 30 nm and 1 ?m by means of Rutherford Backscattering Spectrometry (RBS). An excellent single crystalline quality of all layers was found by RBS channeling measurements as required for photonic applications. The strain relaxation in our layers was evaluated by high resolution X-Ray diffraction reciprocal space mapping (HR-XRD RSM). Strain relaxation as high as 68 % in thick GeSn layers was found for high Sn concentration of 14 at.%. The higher strain relaxation in thicker layers leads to a linear increase of the surface roughness up to a maximum RMS value of 5 nm without the observation of GeSn islands even for thick layers as shown by atomic force microscopy (AFM). The morphology is furthermore investigated by Transmission Electron Microscopy. Room temperature photoluminescence measurements evidence the high optical quality of the GeSn layers with band gaps as small as 0.4 eV and their potential for optoelectronics. Our results demonstrate the possibility of fabricating strain relaxed GeSn alloys of high crystalline quality.

J.15.3
17:15
Authors : T. Grzela(1), W. Koczorowski(2)(3), K. Seweryniak(3), G. Capellini(1)(4), R. Czajka(3), N. Curson(2), T. Schroeder(1)(5)
Affiliations : (1) IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany; (2) London Centre for Nanotechnology, University College London, 17-19 Gordon Street, London, UK; (3) Institute of Physics, Poznan University of Technology, Nieszawska 13A, 60-965 Poznan, Poland; (4) Dipartimento di Scienze, Università degli Studi Roma Tre, Viale G. Marconi 446, 00146 Roma, Italy; (5) Brandenburgische Technische Universität, Konrad-Zuse Str. 1, 03046 Cottbus, Germany;

Resume : Extending the performance of existing Si microelectronics beyond the limits faced by either miniaturization (“More Moore”) or available functions (“More than Moore”) requires the integration of new materials. Germanium, due to its superior physical properties with respect to Si in terms of optoelectronics and its CMOS processing compatibility, is one of the most promising materials to further develop the existing Silicon platform. A key element to achieve high performance Ge device integration is the control over Ge surface chemistry and physics. Certainly, such knowledge will be essential to achieve low resistance metal contacts to Ge devices where high current densities need to be applied (e.g. in Ge MOSFETS and Ge laser diodes). Different metal/Ge systems present promising electrical properties, but ‐ given wide‐spread use in Si CMOS technologies in form of their respective silicides-, cobalt- and nickel- germanides are of special importance. Here, we focus our investigations on the systematic and comparative studies between Co/Ge and Ni/Ge systems. Combined STM, LEED, TEM-EDX and XPS techniques were used to investigate the influence of post evaporation annealing treatments at various temperatures on the structural properties of a few monolayers of metal which were deposited at room temperature on Ge(001) substrates, an approach intended to mimic typical cleanroom processes of metal contact formation in Si microelectronics.

J.15.5

No abstract for this day

No abstract for this day


Symposium organizers
Giovanni CAPELLINI Dipartimento di Scienze / Università Roma Tre

Via della Vasca Navale 84 00146 Roma Italy

+390657333429
capellini@fis.uniroma3.it
Jean FOMPEYRINEIBM Research GmbH

Sauemerstrasse 4 CH-8803 Rueschlikon Switzerland

+41(0)44 724 8387
jfo@zurich.ibm.com
Roger LOOIMEC

Kapeldreef 75 B 3001 Leuven Belgium

+32 16 281 404
roger.loo@imec.be
Thomas SCHROEDER Leibniz Institute for Innovative microelectronics (IHP)

Im Technologiepark 25 15236 Frankfurt (Oder) Germany

+49 / 335 / 5625 – 318
schroeder@ihp-microelectronics.com