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2015 Spring

Materials for Advanced Electronics


Nanomaterials and processes for advanced semiconductor CMOS devices

Following the success of the previous symposia on materials and devices for post-Si CMOS, this symposium will bring together scientists and engineers working towards the integration, materials, processing, and characterisation of high-mobility material devices with advanced CMOS logic.




Due to the performance and economic benefit obtained by scaling, future semiconductor electron devices for logic functions will progress toward ultra-thin-body channels. The benefit is that small devices can be made that yield higher performance and greater energy-efficiency.

However, in order to continue scaling trends, new high mobility channel materials, along with thin-body device architectures (ultra-thin SOI, double or tri-gate multi-gates, nanowires) will have to be introduced. Over the last couple of years FinFETs have become mainstream but still comprise of Si and SiGe channels. The next large steps that are foreseen are the introduction of III-V and Ge channel materials. One possibility after FinFETs is the vertical gate-all-around device architecture.

The biggest challenges for future logic device technologies involve material and process solutions (such as novel contact and doping techniques) for low access resistance in vertical nanowires and other thin-body semiconductor devices. These devices will not be technologically relevant if the high-mobility benefit is swamped by losses due to access resistances. Another grand challenge of our time includes the processing, integration, and understanding of 2D materials such as transition metal di-chalcogenides (TMDs).

Finally, accurate modeling of the above mentioned effects is becoming a critical element for the development of advanced semiconductor devices. With the potential introduction of many new materials and device architectures, physical simulations (ab-initio, molecular dynamics, lattice/on-lattice kinetic Monte Carlo as well as partial differential equations) can help explore the new device options by assisting or replacing experiments.


Hot topics to be covered by the symposium:


  • Materials and processing for thin-body devices based on SOI and high-mobility materials.
  • Substrate fabrication : epitaxial growth, layer transfer, nanowire synthesis and integration.
  • 2D materials (TMD): tuneability, contacting, and devices.
  • Advanced doping methods, including in-situ, PIII, laser annealing, monolayer doping.
  • Dopant activation and diffusion issues in electronic nanomaterials.
  • Defect formation, evolution and engineering, phase transitions.
  • Contact formation in new device architectures and materials.
  • Characterisation issues. 3D, chemical, and electrical profiling.
  • Simulation and modeling of above phenomena (from ab-initio to TCAD).


Confirmed list of invited speakers:


  • L. Czornomaz (IBM-Zurich) "III-V materials and devices for CMOS"
  • J. Holmes (Univ. Cork) "Bottom-up nanowires for device applications”
  • G. Duesberg (Trinity College, Dublin) "Electronic Devices with 2D materials”
  • W. G. van der Wiel (University of Twente) "Molecular Monolayer Doping"
  • C. Hatem (AMAT, USA) "Doping methodologies for future technologies"
  • F. Cristiano (LAAS-CNRS Toulouse), "Defect evolution and dopant activation in Si and Ge"
  • H. Bracht (Univ. Munster) "Diffusion mechanisms and point defect engineering in Ge"
  • N.E.B. Cowern (Univ. Newcastle) "New defect concepts in semiconductors"
  • I. Thayne (Glasgow University) "High mobility material processing, contacts, test structures"
  • W. Vandervorst (IMEC) "Material characterisation from 0D to 3D"
  • I. Martin-Bragado (IMDEA, Madrid) "Atomistic modelling of epitaxial growth of semiconductor materials"
  • D. Esseni (Univ. Udine) "Challenges and opportunities for innovative material systems in CMOS transistors and Tunnel FETs"


Confirmed list of scientific committee members:


  • A. Claverie (France)
  • J. Fompeyrine (Switzerland)
  • G. Impellizzeri (Italy)
  • K.S. Jones (USA)
  • D. Mangelinck (France)
  • A. Nylandsted Larsen (Denmark)
  • L. Pelaz (Spain)
  • P. Pichler (Germany)
  • F. Priolo (Italy)
  • W. Skorupa (Germany)
  • M. Takenaka (Japan)
  • A. Thean (Belgium)




The papers will be published in Materials Science in Semiconductor Processing (Elsevier).

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Authors : Ray Duffy (1), Enrico Napolitani (2), Nikolas Zographos (3), Mark van Dal (4)
Affiliations : (1) Tyndall National Institute, University College Cork, Lee Maltings, Dyke Parade, Cork, Ireland. (2) MATIS IMM-CNR, Department of Physics and Astronomy, University of Padova, Via Marzolo 8, Padova, Italy (3) Synopsys Switzerland LLC, Thurgauerstr. 40, Zurich, Switzerland. (4) TSMC Europe BV, ATRD (Advanced Transistor Research Division), Kapeldreef 75, Leuven, Belgium.

Resume : Opening remarks for Symposium Z.

Authors : Chien-Chao Huang, Ta-Wei Wu, 1Je-Chuan Shue, 1Ming-Yi Li, 2Yu-Zen Tasi, and Ming-Pei Lu
Affiliations : National Nano Device Laboratories, Hsinchu 300,Taiwan 1Dept of Materials Eng. and Science, University of Tsing-Hua, Hsinchu, Taiwan 2Dept. of Electronic, University of Cheng-Shiu, Kaohsiung, Taiwan

Resume : The SiGe channel materials and nanowire architecture are still regarded as one of the most promising candidates for the sub-10nm node CMOS logic technology. The geometry of rectangle nanowires caused the presence of high electrical field near the edge corners, resulting in poor control ability of electrical performance and the degradation of high-field mobility of the inversion carriers according to the result of simulation. In this work, both triangle-like and circle-like shapes of nanowire geometry were proposed to reduce the corner effect, especially highlighting the circle nanowires with more uniform electric field and absence of the corner effect. The two geometry formation of nanowires utilizes the conventional lithography and etching process to create specific profile for subsequent Si migration process. With proper gas flux control, the typical pressures of H2 gas were in the range of 10-2 torr. The Si migration was reproducibly fabricated with the certain conditions of the annealing temperature and time. Both circle and triangle shapes of nanowires were fabricated on SOI wafer with optimum patterning process. An enhancement technology of drain current was to implement the heterostructure of p-MOSFET which consisted of a Si buffer layer, a strained-SiGe channel layer, and finally a top Si cap layer on Si substrate. In addition to, the analytic result of diffusion model was successfully developed to predict the Ge diffusion behavior verified by the Ge profile of SIMS result. Finally, the ID-VG characteristics of a 28nm circle-like Si nanowires demonstrated an excellent subthreshold swing (less than 100mV/dec) and the mobility of strained-SiGe channel was improved more than 50% than that of Si channel.

2D Materials : Justin Holmes
Authors : Georg S. Duesberg 1, 2, Nina C. Berner2, Riley Gatensby1, 2, Toby Hallam2, Hye-Young Kim2, Kangho Lee2, Niall McEvoy2, Hugo Nolan1, 2, Maria O’Brien1, 2, Ehsan Rezvani1, 2, Sinéad Winters1, 2, Christian Wirtz1, 2, Chanyoung Yim1, 2
Affiliations : 1 School of Chemistry, Trinity College Dublin, Ireland 2 Centre for Adaptive Nanostructures and Nanodevices(CRANN)& Advanced Materials BioEngineering Research Centre(AMBER), Trinity College Dublin, Ireland

Resume : The reduction of dimensionality has revealed exciting properties in layered 2D materials such as graphene and transition metal dichalcogenides (TMDs). To integrate these materials into hybrid devices with conventional semiconductors, processes for reliable large scale synthesis, functionalisation and contacting must be developed. Synthesis of large scale TMD film with methods compatible semiconductor production lines will be discussed. We present the thermally assisted conversion (TAC) of various metal layers to their sulfides and selenides. The samples are produced on silicon chips and were subjected to structural and spectroscopic characterization. We have good control over their thickness and morphology. Further is possible to structure and electrically address the films yielding simple devices such as transistors, diodes and sensors. Further we report on the direct CVD growth on SiO2 of MoS2 and WS2 monolayer films in a micro-reactor set-up. The highly crystalline TMDs were also tested in simple transistor configurations. Further chemical functionalisation of TMD layers on silicon are presented, which will be crucial for their integration and passivation.

Authors : A. Piazza (1,2,3), S. Agnello (2), G. Fisichella (1), G. Greco (1), S. Di Franco (1), A. La Magna (1), R. Lo Nigro (1), F. Roccaforte (1), F. Giannazzo (1)
Affiliations : (1) CNR-IMM, Catania, Italy (2) Department of Physics and Chemistry, University of Palermo, Italy (3) Materials Science and Nanotechnologies PhD School, University of Catania and University of Palermo, Italy

Resume : Layered semiconductors, such as MoS2, recently attracted considerable interest as potential candidates for post-Si CMOS technology. In spite of the very promising performances (On/Off current ratio >1e7 and subthreshold swing >70 mV/decade) of the first monolayer MoS2 transistors, several processing issues (Ohmic contacts, gate dieletrics, passivation, doping) need be addressed to fully exploit MoS2 potentialities. Source/drain contact resistances strongly impact the electrical characteristics of MoS2 transistors, leading to severe underestimation of field effect mobility. Several metal contacts, including graphene (Gr), are under investigation for contact resistance reduction. In this work, the current injection mechanisms from metals with different workfunctions (Ti, Ni, Pt, Au..) and from Gr contacts to thin films of MoS2 have been investigated by conductive atomic force microscopy (CAFM) and by transmission line model (TLM) test structures. MoS2 films with large size (up to ~100 um) and variable thickness (2-50 nm) were transferred to SiO2/Si by thermo-compression printing. Temperature dependent electrical characterization of back-gated TLM structures allowed to disentangle the channel resistance from the contact resistance contribution and to get information on the current injection mechanism from metal to MoS2. Nanoscale resolution CAFM analyses provided further insight on the lateral uniformity of the current injection and its impact on the average contact resistance.

Authors : Ioannis Deretzis, Rossella Di Giugno, Salvatore Francesco Lombardo and Antonino La Magna
Affiliations : Consiglio Nazionale delle Ricerche, Istituto per la Microelettronica e Microsistemi Z.I. VIII Strada 5 I 95121 Catania Italy

Resume : Kinetic Lattice Monte Carlo approach is applied to the multi-scale atomistic simulation of the graphene growth on different substrates. The stochastic simulation method is coupled to the continuum simulation of the kinetics and the reactions in the gas phase occurring in the equipments. Chemical Vapour Deposition (CVD) and selective Si evaporation synthesis techniques are considered on metal (Cu) and silicon carbide (SiC) substrates respectively. In the latter case the inner structural transition from the SiC to the graphene structure is also simulated. Kinetics of the deposited atomic layer kinetics proceeds by islands' nucleation and (Ostwald ripening type) growth in the case CVD processes; whilst structural transition from SiC to graphene is mediated by not-ordered weakly bounded carbon-carbon configurations in the carbon rich regions generated by the selective Si sublimation. Quantitative predictions of the process evolution in term of crystal state and defects' generation as a function of the initial state and the process's parameters (temperature, pressure, gas flows) can be obtained and readily compared with experimental structural characterization of processed samples. Preliminary results on the simulation of the N dopant incorporation during the growth will be also discussed.

Authors : B. Hähnlein1, A. Alsioufy1,2, M. Lootze1,2, F. Schwierz2, J. Pezoldt1
Affiliations : 1FG Nanotechnologie, Institut für Mikro- und Nanotechnologien MacroNano®, Technische Universität Ilmenau, Postfach 100565, 98684 Ilmenau, Germany; 2FG Festkörperelektronik, Institut für Mikro- und Nanotechnologien MacroNano®, Technische Universität Ilmenau, Postfach 100565, 98684 Ilmenau, Germany

Resume : The ongoing miniaturization of electronic devices led to structural dimensions in the low nanometer range. Growing complexity of the devices itself and increasing requirements on the technology make the fabrication of field effect transistors expensive and fault-prone. Compared to conventional semiconductors two dimensional materials offer advantages in device scaling. In the field of these materials like graphene or MX2 much experience was gained in the last years. In contrast to conventional top- and double-gate field effect transistors 2D materials allow easily the manufacturing of planar structures. The great advantage of a planar design is the lack of need of a gate oxide which eliminates effects on the channel mobility and avoids the challenges occurring by depositing a gate stack on a channel material containing a two dimensional electron gas. In this work, three terminal junctions and side gate transistors based on graphene and molybdenum disulphide are presented. The graphene devices were fabricated based on an all carbon technology on silicon carbide substrates, whereas the molybdenum disulphide was fabricated using the exfoliation technique. It will be demonstrated that the properties of planar structures are comparable to conventional MOSFETs. The influence of the device design on the device properties will be demonstrated.

Authors : C. Bazioti1, G. P. Dimitrakopulos1, Ph. Komninou1, K. Aretouli2, P. Tsipas2, D. Tsoutsou2, E. Xenogiannopoulou2, A. Dimoulas2
Affiliations : 1Physics Department, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece; 2Nanoscience and Nanotechnology, NCSR DEMOKRITOS, 15310, Athens, Greece

Resume : The structure of two-dimensional (2D) selenide films is studied by high resolution transmission electron microscopy (HRTEM). Ultrathin films of MoSe2 and Bi2Se3 were deposited on (0001)AlN/(111)Si templates by molecular beam epitaxy (MBE). High quality large scale MoSe2 films on a wide band gap substrate are promising for novel nanoelectronic devices, and enhanced functionality can be obtained by combination with the topological insulator properties of Bi2Se3. The MoSe2 films were deposited either directly on AlN or on the Bi2Se3 layers. A good epitaxial relationship was determined between film and substrate, and heteroepitaxial interfaces retained a crystalline structure despite the van der Waals bonding. Similar interfacial quality was not achievable when Bi2Se3 was deposited directly on silicon. HRTEM was combined with image simulation in order to elucidate imaging conditions for dissimilar materials. Strain measurements were performed by geometrical phase analysis in order to determine variations in lattice spacings. The high quality crystalline structure of the MoSe2 films was attested by the lack of extended defects. Vertical and in-plane 180o rotational domain boundaries were found in the Bi2Se3 layers. The structural observations were corroborated from angle-resolved photoelectron spectroscopy measurements. Acknowledgement: Work supported by the ERC Adv. Grant SMARTGATE-291260- and the National program of excellence (ARISTEIA-745) through project TOP-ELECTRONICS.

III-V processing and devices I : David Esseni
Authors : Iain Thayne
Affiliations : School of Engineering, University of Glasgow, Glasgow G12 8LT

Resume : III-V materials are being increasingly used in energy efficient electronics such as narrow bandgap In(Ga)As MOSFETs for continued scaling of Moores Law and in large bandgap GaN power electronics. This presentation will review recent activity in both narrow and large bandgap III-V devices. Emphasis will be placed on the development of silicon-compatible approaches to process module development, and integration strategies. The presentation will cover a number of themes including III-V materials, the impact of etching processes for non-planar InGaAs devices; source-drain contacts for InGaAs and GaN-based devices; gate stacks including high-k dielectrics; and the challenges of integrating these using silicon-compatible approaches to realise energy efficient electronic devices.

Authors : Andrey Sarikov, Ignacio Martin-Bragado
Affiliations : IMDEA Materials Institute. Eric Kandel 2, 28906, Getafe, Madrid, Spain

Resume : III-V structures formed by epitaxial growth become more and more popular nowadays to be integrated into existing microelectronic devices (e. g. traditional Si based devices) with the aim of the enhancement of their capabilities. Such structures may be formed by e. g. metal organic chemical vapor deposition (MOCVD), which is currently one of the most attractive and popular methods for III-V epitaxy. At this, the control over the formation of desired structures requires understanding the mechanisms behind the epitaxial process as well as the knowledge about its characteristics. In this work, the characteristics of the MOCVD epitaxial growth of III-V compounds are studied by numerical simulation and kinetic Monte Carlo modeling. According to the typical experimental conditions, growth is accepted to be determined by group-III elements. A model considers macroscopically the kinetics of the transport of group-III element precursors in the gas phase through the diffusion layer towards the substrate and their decomposition on the substrate surface with subsequent group-III element adsorption. Lattice Kinetic Monte Carlo (LKMC) method is used to model the kinetics of epitaxial layer growth by atom incorporation taking into account the interaction with neighboring atoms up to third nearest neighbors. As a result of a combined approach, the growth rate of III-V epitaxial layer is derived as a function of experimental conditions (group-III precursor partial pressure, temperature, substrate orientation) as well as of the characteristics of the systems used (precursor diffusivity in the gas phase and decomposition rate, energy of adsorbed atom interaction with neighboring atoms etc.), and the time. The model is calibrated by comparing the model predictions with available experimental data. Physical mechanisms influencing on the formation of the growth rate of III-V epitaxial layers are described. Obtained results are useful for the elaboration of the technologies for the novel types of microelectronic devices based on III-V epitaxial structures.

Posters - Symposium Z : -
Authors : T. Bentrcia1, F. Djeffal2, Z. Dibi2 and D. Arar2
Affiliations : 1) Department of Physics, University of Batna,Batna 05000, Algeria. 2)LEA, Department of Electronics, University of Batna, Batna 05000, Algeria. E-mail:,, Tel/Fax: 0021333805494

Resume : Multi-Gate Junctionless MOSFETs are promising devices to overcome the undesired short channel effects for low cost nanoelectronic applications. However, the use of uniformly doped channel, source and drain regions presents the well-known problem of the high series resistance associated to the extensions, which degrades the electrical performance of the device. Therefore, in order to obtain a global view of Double-Gate Junctionless (DGJ) MOSFET performance under critical conditions, new designs and models of nanoscale DGJ MOSFET including analog performance are important for the comprehension of the fundamentals of such device characteristics. Based on numerical investigation of a nanoscale DGJ MOSFET, in the present paper a numerical investigation for I-V and small signal characteristics by including the highly doped extension regions is presented. The proposed approach, which is a technologically feasible technique by introducing only one ion implantation step, provides a good solution to improve the drain current and small signal parameters at high gate and drain voltages for analog applications. In this context, I-V and analog characteristics of the proposed design are investigated by 2-D numerical modeling and compared with conventional DGJ MOSFET characteristics.

Authors : Sung Yong Kang, Han Gil Na, Yong Jung Kwon, Hong Yeon Cho, Hyoun Woo Kim*
Affiliations : Department of Materials Science and Engineering, Hanyang University, 222 Wangsimni-ro, Seongdong-Gu, Seoul, 133-791, Korea

Resume : Silicon nanowires (SiNWs) have a variety of advantages over the other nanomaterials, because they can be easily fabricated by well-developed VLSI process. Furthermore, their electrical properties can be easily modified by the doping. In addition, SiNW will have great advantages over their bulk counterpart, due to the three-dimensional geometry. In this paper, we report on the successful fabrication of SiNWs, by a novel, simple, and low-cost method. We prepared SiNWs in a short step by chemical etching of crystalline silicon in HF/H2O2/AgNO3 aqueous solution, in which metal nanoparticles acted as an etch mask. The SiNWs’ diameter and length depend on the H2O2/AgNO3 concentration and dissolution time. The SiNWs were investigated by scanning electron microscopy (SEM), transmission electron microscope (TEM) and x-ray diffraction (XRD). The SiNWs sensors exhibited an excellent performance with respect to hydrogen concentration. We have discussed the related sensing mechanisms.

Authors : Minhyeong Lee, Sangmo Koo, Eunjung Ko, Hyunchul Jang, Dae-Hong Ko
Affiliations : Yonsei University

Resume : To reduce the source/drain contact resistance in nMOSFET devices, in-situ phosphorus doping process has been used widely. While ion implantation process needs post annealing treatment for the activation of dopant and the removal of surface defects, in-situ doping process could fabricate the source/drain region which has uniform dopant concentration without the additional thermal processing. However, in case of highly phosphorus doping, the deposition rate of Si films drastically decreases, because phosphine (PH3) not only blocks the preferable sites for Si adsorption but also strongly hinders the hydrogen desorption process. In this study, in-situ phosphorus-doped epitaxial layers were grown by using ultra-high vacuum chemical vapor deposition (UHV-CVD) on the blanket bare and patterned Si wafers. For low resistivity, we investigated the optimized condition that enhances the incorporation of phosphorus in epitaxial layer as well as suppresses the reduction of the deposition rate of that. The source gases are disilane (Si2H6) and phosphine (PH3, 1% in He). The analysis of the microstructure was conducted by high resolution transmission electron microscopy (HR-TEM) and phosphorus concentrations were measured in secondary ion mass spectroscopy (SIMS) depth profile experiments.

Authors : B.E.Umirzakov, D.A.Tashmukhamedova, S.B.Donaev, M. Yusupdjanova
Affiliations : Tashkent state technical university

Resume : In work are studied with use of methods of secondary and photoelectronic spectroscopy the structure, optical and electronic properties of a surface of films CaF2/Si(111) implanted by ions of active metals. The analysis of structure and spectra of photoelectrons together with data Auger electron spectroscopy and RHEED, have shown, that in the process of implantation ions of Ва + in films CaF2 is accompanied disordering at the surface layer, formation of new connections (approximately 15-20% of atoms Ва implanted at the surface layers formed connections of type Ba+F, Ba+Ca+F) and surface enrichment by unconnected atoms of barium. In area energy ions Е0=3÷5 keV the share of atoms of the alloying element entering into a chemical bond with atoms of a matrix, can increase to 25÷30 ат. % (here for 100 ат. % the general concentration of the implanted impurity) is accepted. Annealing of this system leads to a redistribution of atoms Ва and crystallisation at the surface layer, to increase in a share of atoms Ва forming a chemical bond with atoms of a matrix. At temperature Т=1000 K all atoms of barium are included into a chemical bond with atoms of a matrix and formed an epitaxial film Ва1-хСахF2 from a reconstructed constant lattice. Thus on a surface connections of type Ba0.6Ca0.4F2 with a constant lattice ~5.73Å.

Authors : D.A.Tashmukhamedova, B.E.Umirzakov, X.X.Boltaev, Y.S.Ergashov
Affiliations : Tashkent state technical university

Resume : It is known, that nanodimensional structures created on a surface of solid bodies are possess new, not characteristic properties for massive materials. Special interest represent nanoporous films on a basis oxide silicon and silicides of the metals generated on a surface of silicon which have prospects in integrated microcircuits, magnito-electronic devices, optoelectronic devices [1-3]. In the given work are studied the composition, structure and properties nanocluster phases and nanofilms SiО2 received by a method of implantation dioxide ions( ) in Si with a variation of energy and an irradiation dose. In particular it is shown, that at doses D = 8?1015 - 4*1016 cm-2 located nanoareas Si. Presence such nanoarea after annealing at Т = 1200 - 1250 K allows to receive nanofilms Si on surface SiO2, consequently is formed the three-layer system of type Si - SiO2 - Si (111). References 1. V.I. Rudakov, J.I. Denisenko.,V.V. Naumov, S.G. Simakin//Microelectronics. 2011. V. 40. № 6.pp. 424 - 429. 2. M.V. Gomojunova, G.S. Grebenjuk, I.I. Pronin //Magazine of technical physics. 2011. V. 81. №11.pp. 130 - 134. 3. V.G. Lifshits // Electron spectroscopy and nuclear processes on a silicon surface.-М: the Science, 1985. - 200 p.

Authors : Ihab Eddine Yahiaouia1*, Yahia Bourourou1, Mohamed Amine Benali2
Affiliations : 1Modelling and Simulation in Materials Science Laboratory, Physics Department, University (UDL), Sidi Bel-Abbes, Algeria; 2Laboratory of Elaboration and Characterization of Materials, University of Sidi Bel-Abbes, Sidi Bel-Abbes, Algeria

Resume : Since the discovery of the spintronic a new field has emerged, the half-metallicity investigation to several classes of compounds like Heusler alloys. In this paper the calculations are performed by a developed full-potential augmented plane wave method (FP-LAPW) within density functional theory (DFT), as exchange?correlation potential we used the LSDA U. The full-Heusler Co2VSi alloy crystallize in the cubic L21 structure, shows a Slater-Pauling behavior and follows the Mtot = (Ztot ? 24) rule. Moreover, the calculation of the densities of states (DOSs) of Co16V1-xErxSi8 (x= 0.25) compounds show that the half-metallic properties are completely conserved when the substitution of Er in the V sites are done, this effect being determined through the impurity (4f) Er with (3d) V coupling itinerant electron spins for FM and AFM states. Our results are in agreement with the literature.

Authors : R. Boussaha, H. Fitouri, A. Rebey, Z. Chine, B. El Jani
Affiliations : University of Monastir, Faculty of Sciences, Unité de Recherche sur les Hétéro-Epitaxies et Applications, 5019 Tunisia.

Resume : There is substantial interest in developing new classes of semiconductor materials exploiting the properties of group V semimetal bismuth. These include materials for development of optoelectronic, thermoelectric and electronic devices such as laser diodes, light emitting diodes and solar cells. The effect on the growth kinetics of the dilute GaAsBi and InAsBi nanostructures, caused by incorporating Bi in GaAs and InAs, was examined at different temperatures. The formation of well-ordered metallic Bi/III-V was obtained and the Bi adsorption on GaAs surface was studied. Structural properties of dilute III-V bismide nanostructures were studied by scanning electronic microscopy (SEM) and atomic force microscopy (AFM). These analyses established that the nucleation and growth mechanism of dilute III-V bismide was carried out under a 3D mode. At low growth temperature, a Bi-induced nanoline structure in the InAsBi surface was observed. The main reason to stabilize the nanolines was found to be the large atomic size of Bi. The obtained results have shown a new window for III-V nanowires growth with bismuth as a catalyst.

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Advanced doping and contacts : Mark van Dal
Authors : Wilfried Vandervorst
Affiliations : Senior Fellow, Director materials and components analysis department, Imec

Resume : Developing and implementing next technology nodes is a complex task involving innovation in materials engineering, process development and device design. Metrology is now recognized as an important enabler within the development paths of novel technologies and also a crucial component for their manufacturing implementation. The gap between metrology for device and material development (lab based) versus manufacturing (lab based) has traditionally been very large as they were acting frequently on very different length scales (for instance blanket versus device analysis), with different response times and amount of data. The down scaling of devices into non-planar structures has led to physical phenomena which can only been seen in 3D-structures and confined volumes such that the lab based metrology is now pushed into dealing with device dimensions and expands rapidly into atomic scale metrology. (Fab) Metrology linked to manufacturing of next generation technologies also needs to address the specificity of nano-scaled devices and similarly requires a shift towards high spatial resolution analysis, be it that the volume and speed requirements interfere with some of the solution proposed in the lab. We will provide an overview of novel developments addressing atomic scale analysis in logic and memory devices as well as new approaches towards high spatial resolution analysis suitable for high volume analysis while matching the technology requirements.

Authors : Tai-Chun Kuo,Wen-Hsi Lee
Affiliations : National Cheng-Kung University

Resume : In order to fabricate ultra-shallow junction (USJ) for 20nm IC node application, a low energy (400eV) ion implantation and a novel microwave annealing technique with two steps for the solid phase epitaxy regrowth and activation of boron dopants in silicon were used in this study. In the first step annealing, a 2.4 kWatt(~500℃) high power microwave annealing was used to re-growth the amorphous layer with PAI treatment of Ge (20keV @5e14 atoms/cm2) into crystal silicon. The activation energy (2.3 eV) to attain rapid lattice restoration for the solid phase epitaxy regrowth by microwave annealing is lower than that by the conventional RTP. In the second step annealing, since the crystalline silicon has high absorption efficiency to microwave, a 0.6 kWatt(~250℃) low power microwave annealing is able to activate implanted boron in silicon (400eV @1e15 atoms/cm2 ), and decrease the resistance to 436 ohm. / sq without diffusion. We have successfully demonstrated that the novel ultra low temperature microwave annealing technique is promising for improvement on P-MOS performance. The on/off current ratio (Ion/off) of the P-MOS is more than 2x106 (VDS = -0.05 V). The low resistance of 436 ohm./ sq after activating by 250℃ microwave annealing is reflected to the high performance of P-MOS with a lower S.S.(-92.59mV) ,and a high hole mobility27.5cm2/V-S.

Molecular Monolayer Doping : Wilfried Vandervorst
Authors : Wilfred G. van der Wiel
Affiliations : NanoElectronics Group, MESA+ Institute for Nanotechnology, University of Twente, P. O. Box 217, 7500 AE Enschede, the Netherlands

Resume : Molecular monolayer doping (MLD) presents an alternative to achieve doping of silicon in a nondestructive way, and holds potential for realizing ultra-shallow junctions and doping of non-planar surfaces. Here, we report the mixing of dopant-containing alkenes with alkenes that lack this functionality, at various ratios to control the dopant concentration in the resulting monolayer and concomitantly the doping dose in the silicon substrate [1]. The mixed monolayers were grafted onto hydrogen-terminated silicon using well-established hydrosilylation chemistry. Contact angle measurements, X-ray photon spectroscopy (XPS) on the boron-containing monolayers, and Auger electron spectroscopy on the phosphorus-containing monolayers show clear trends as a function of the dopant-containing alkene concentration. Dynamic secondary ion mass spectroscopy (D-SIMS) and Van der Pauw resistance measurements on the in-diffused samples show an effective tuning of the doping concentration in silicon. [1] L. Ye, S.P. Pujari, H. Zuilhof, T. Kudernac, M.P. de Jong, W.G. van der Wiel and J. Huskens, accepted for publication in ACS Applied Materials & Interfaces.

Authors : Rosaria A. Puglisi, Sebastiano Caccamo, Luisa D’Urso*, Gabriele Fisichella, Filippo Giannazzo, Markus Italia and Antonino La Magna.
Affiliations : Consiglio Nazionale delle Ricerche, Istituto per la Microelettronica e Microsistemi, Strada Ottava 5 Zona Industriale 95121,Catania, Italy. *Dipartimento di Scienze Chimiche, Università degli Studi di Catania, Viale Andrea Doria 6, Catania.

Resume : Molecular doping of semiconductors is a rapidly growing area because it provides a simple, scalable and cost-effective alternative to standard fabrication methods and additionally allows conformality on structured surfaces. During this process the molecule chemically bonds to the target surface with a self-limiting process ruled by its steric properties. Thermal process performed after the formation of the self-assembled layer drives the diffusion of dopant atoms inside the substrate matrix. The technique allows the formation of n- or p- type doped Si, by properly selecting the precursor source [MATER SCI ENG B 178 (2013) 686], doping on structured surfaces [Phys. Stat. Sol. A 210 (2013) 1564] and fabrication of Si nanowire based solar cells [Sol. En. Mat. Sol. Cells 132 (2015) 118]. Most of the work on molecular doping lacks of information on the molecule / Si interface chemical properties, on the mechanisms of the molecule evolution during the coating and the diffusion step. Moreover it has so far been devoted to the molecules design to tune the final dopant dose and distribution. We present results on the interface characteristics and evolution, also in terms of mono- and multi-layers formation and on the doping features, such as junction depth, carrier dose and sheet resistance, carried out by fixing the dopant precursor and varying the coating conditions.

Authors : Giuseppe Alessio Verni, Maart Van Druenen, Brenda Long, Gillian Collins, Ray Duffy, Justin D. Holmes
Affiliations : University College Cork; University College Cork; University College Cork; University College Cork; Tyndall National Institute; University College Cork

Resume : The advent of non-planar device architectures, along with device scaling, has created the need for a radically new, conformal and preferably non-destructive method for doping semiconductors. Molecular layer doping (MLD) has recently been shown to be an effective, chemical approach for doping semiconductor substrates and nanodevices, e.g. FinFETs, without causing crystal damage as seem with traditional ion-bombardment techniques. MLD comprises two steps: i) functionalisation of the semiconductor surface with a p- or n- dopant containing molecule and ii) thermal diffusion of the dopant atoms, by rapid thermal annealing, into the semiconductor. However, as electronic devices are scaled towards smaller dimensions, further optimisation of MLD processes are required, e.g. to achieve a carrier concentration >10^20 at/cm^3 at really shallow depths (< 20 nm). The depth to which dopants can be driven, and controlled, by thermal annealing has however proven to be a difficult task, particular in high mobility semiconductors such as Ge. To-date, there have only been a few reports of shallow doping by MLD in Si. This presentation describes the use of different surface functionalisation approaches, in particular the application of spacer molecules, and advanced annealing techniques to control the diffusion depth of dopants in Ge by MLD. AFM, XPS and ECV analysis of phosphorous-doped Ge substrates, as well as TEM and electrical measurements of Ge nanowire devices will be presented.

Authors : F. A. Geenen, K. Van Stiphout, J. Jordan-Sweet, A. Vantomme, C. Lavoie, C. Detavernier
Affiliations : Ghent university, Dept. of Solid-State Physics, Krijgslaan 281/S1, 9000 Ghent, Belgium; KU Leuven, Instituut voor Kern- en Stralingsfysica, Celestijnenlaan 200D, 3001 Leuven, Belgium; IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, USA; KU Leuven, Instituut voor Kern- en Stralingsfysica, Celestijnenlaan 200D, 3001 Leuven, Belgium; IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, USA; Ghent university, Dept. of Solid-State Physics, Krijgslaan 281/S1, 9000 Ghent, Belgium;

Resume : The influence of Al on the phase formation between Ni and Si(001) was investigated by altering the Al concentration and the Ni thickness. In a first series of samples, 20 nm Ni on a Si (001) substrate was alloyed between 0 and 50 at. % Al. The phase formation was examined during heating by sheet resistance and XRD. Small additions of Al (0- 28%) in the Ni layer result in a mono-silicide layer that is far more stable towards agglomeration. Polefigure measurements indicate that the axiotaxial texture of NiSi is less prominent and that the grain size is smaller when compared with silicides originating from pure Ni. When heated to higher temperatures, these samples form an epitaxial layer, identified as NiSi2. Without the addition of Al, NiSi2 is known to grow in two epitaxial orientations. When Al is added, the orientation defined by NiSi2(1-22)//Si(001) and NiSi2(1-10)//Si(101) is hindered, possibly causing a smoother interface with the Si substrate. Adding more than 30 at.% of Al results in a highly different phase formation where no NiSi formation could be observed. A second series of samples investigated the addition of Al for Ni films thinner than 10 nm. Ultrathin Ni layers are known to react directly into an epitaxial NiSi2 phase without first forming NiSi. When alloyed with Al, the critical thickness for this phenomenon to occur is elevated from 4-5 nm to 8 nm, indicating that the addition of Al is beneficial for the growth of epitaxial NiSi2.

Authors : Woo Sik Yoo1, Takeshi Ueda1, Toshikazu Ishigaki1, Kitaek Kang1 and Victor Vartanian2
Affiliations : 1WaferMasters, Inc.;2SEMATECH

Resume : Performance enhancement of MOSFETs is realized by introducing appropriate levels of strain in silicon. Stress in Si in various directions results in localized strain fields and affects the silicon piezoresistance coefficients. Tensile stress in a silicon channel increases electron mobility while compressive stress increases hole mobility. Uniaxial compressive strain is typically generated by embedding SiGe into the source/drain region of a device. Development of an accurate and reliable strain/stress characterization technique becomes extremely important for device simulation, design and manufacturing process monitoring and control of advanced MOSFETs. In this paper, stress in isolated Si1-xGex test pads and silicon lines and circles surrounded by Si1-xGex was characterized by a polychromator-based, very high resolution Raman system (WaferMasters MRS-300) as a function of pattern diameters, widths, and pitch. Three major spectral lines (457.9, 488.0 and 514.5 nm) from a multiwavelength Ar ion laser are used as the excitation source. Five patterned Si1-xGex/Si(100) wafers with nominal Ge content in the range of 15~35 at% were characterized. Nominal Si1-xGex layer thickness is ~40 nm. Stress of the Si circles surrounded by SiGe was negligible. For linear arrays with pattern size of 100~300 nm, the Si stress increased with increasing pitch size. For the linear arrays with 500 nm pitch and the blanket area, the Si stress was relatively small and independent of pitch.

Authors : S. Paleari, A. Molle, A. Lamperti, M. Fanciulli
Affiliations : Dipartimento di Scienza dei Materiali, Università di Milano Bicocca, Milano, Italy; Laboratorio MDM, CNR-IMM Agrate Brianza (MB), Italy; Laboratorio MDM, CNR-IMM Agrate Brianza (MB), Italy; Dipartimento di Scienza dei Materiali, Università di Milano Bicocca, Milano, Italy and Laboratorio MDM, CNR-IMM Agrate Brianza (MB), Italy

Resume : We report on the investigation of electrically active defects at the interface between germanium and germanium oxide. Germanium is a promising channel material for high performance CMOS [1], provided the proper material is successfully implemented as gate oxide. In particular, the gate stack comprising a high-k oxide and a GeO2 insulating layer is one of the best options, in terms of scalability and density of interface traps (Dit) [2]. Still, at present the Ge/GeO2 interface is lagging behind the silicon counterpart, mainly due to traps that are not passivated by hydrogen anneal. In this regard, we previously identified the Ge dangling bond (DB) as an electron trap at the interface, by means of electrically detected magnetic resonance spectroscopy [3,4]. In this paper, we present an extensive investigation of Ge/GeO2/Al2O3 MOS capacitors by admittance spectroscopy, revealing the negative-U behavior of interface traps with transition levels about 0.1 eV above valence band edge. This result provides further insight into the reasons of the unsuccessful hydrogen passivation of the traps and the undetectability of Ge DBs by conventional electron spin resonance. [1] R. Pillarisetty, Nature 479, 324–8 (2011). [2] X. Yang et al., Appl. Phys. Lett. 105, 092101 (2014). [3] S. Baldovino, A. Molle, and M. Fanciulli, Appl. Phys. Lett. 93, 242105 (2008). [4] S. Paleari, S. Baldovino, A. Molle, and M. Fanciulli, Phys. Rev. Lett. 110, 206101 (2013).

Authors : Razvan Pascu1,3, Florea Craciunoiu1, Dragos Ovezea2, Marian Badila3, Gheorghe Pristavu3, Gheorghe Brezeanu3, Cosmin Romanitan1,Jenica Neamtu2
Affiliations : 1 National Institute for Research&Development in Microtechnology Bucharest Romania 2 National Institute for Research&Development in Electrical Engineering, Bucharest Romania 3 Politechnica University Bucharest Romania

Resume : The emergence of advanced semiconductor devices, like those based on silicon carbide (SiC) successfully contributes to developing applications for hostile environments. Due to outstanding SiC properties, such as wide band gap, low dielectric constant, high breakdown voltage, good thermal conductivity, chemical stability in reactive environments, SiC sensors are capable of operating properly at high temperatures and hostile environments. In this paper we investigate the temperature influence on the behavior of hydrogen sensors based on MOSiC capacitors which use Pd and Ni as catalytic gates. The structures were fabricated on n-type 4H-SiC Cree wafers, with an active epitaxial layer having a thickness of 7.9 μm, and doping of 2.07E16 cm¬¬¬-3. The oxide layer, with different thicknesses, varying from 10 to 50 nm was thermally grown. A chip structure with three different areas has been developed in order to obtain a sensor array for hydrogen detection. The sensor response, measured on a Pd MOSiC structure, shows an important temperature dependence up to 200°C. After this threshold, the sensitivity remains practically constant. This behavior can be associated with the presence of interface states, which affect sensor sensitivity at low temperatures. Over 200°C, the effect of interface states is diminished by the Fermi level shift into the SiC bandgap.

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Defect evolution and diffusion mechanisms I : Enrico Napolitani
Authors : H. Bracht
Affiliations : Institute of Materials Physics, University of Münster, D-48149 Münster, Germany

Resume : Germanium (Ge) is being actively considered by the semiconductor community as a mainstream material for nanoelectronic applications. Ge has advantageous materials properties; however, its dopant-defect interactions are less understood as compared to the mainstream material, silicon. The understanding of self- and dopant diffusion is essential to form well defined doped regions. Although p-type dopants such as boron exhibit limited diffusion, n-type dopants such as phosphorous, arsenic, and antimony diffuse quickly via vacancy-mediated diffusion mechanisms. In this presentation, experiments on self- and dopant diffusion in Ge are reviewed. Accurate modeling of the experimental profiles provides detailed information about the type and properties of native point defects in Ge and their impact in dopant diffusion. The results deduced from self- and dopant diffusion in Ge confirm the predictions of theoretical calculations. Overall a consistent picture on the diffusion mechanisms and on the properties of the native point defects is obtained that helps to develop efficient defect engineering strategies to restrain dopant diffusion in Ge and to enhance their electrical activation [1]. In contrast to recent results of Cowern et al. [2], no evidence on the existence of different forms of Ge self-interstitials with low and high formation entropies is found. [1] A. Chroneos and H. Bracht, Appl. Phys. Rev. 1, 011301 (2014). [2] N.E.B. Cowern et al., Phys. Rev. Lett. 110, 155501 (2013)

Authors : T. Südkamp, E. Bruno, D. Bougeard, H. Bracht
Affiliations : Institute of Materials Physics,Westfälische Wilhelms-Universität Münster, 48149 Münster, Germany; MATIS CNR-INFM, Università di Catania, Via S. Sofia 64, 95123 Catania, Italy; Institute of Experimental and Applied Physics, University of Regensburg, 93040 Regensburg, Germany; Institute of Materials Physics,Westfälische Wilhelms-Universität Münster, 48149 Münster, Germany;

Resume : Experiments on the diffusion of boron (B) in germanium have been performed under equilibrium [1] and non-equilibrium conditions [2]. The equilibrium diffusion experiments provide a B diffusion activation enthalpy of 4.65 eV for temperatures between 800°C and 900°C that exceeds the activation enthalpy of self-diffusion by 1.5 eV. The high activation enthalpy of B diffusion is considered to indicate a Ge self-interstitial mediated diffusion rather than via vacancies [1]. This seems to be supported by B diffusion under non-equilibrium conditions established by irradiation [2,3]. Theoretical calculations [4] predict a repulsive interaction between substitutional B and vacancies showing that the activation enthalpy of B diffusion via vacancies will also exceed the activation enthalpy of self-diffusion. To clarify the mechanism of B diffusion in Ge we performed additional studies under equilibrium conditions to extend the temperature range and thus to determine the activation enthalpy of B diffusion more accurately. Moreover, the impact of doping on B diffusion is investigated to deduce the charge state of the mobile B species. Finally, the equilibrium diffusion of B is compared to its diffusion behavior under irradiation to deduce a consistent model of B diffusion in Ge. [1] S. Uppal et al., J. Appl. Phys. 96, 1376 (2004) [2] E. Bruno et al., Phys. Rev. B 80, 033204 (2009) [3] S. Schneider et al., Phys. Rev. B 87, 115202 (2013) [4] A. Chroneos, J. Appl. Phys. 107, 076102 (2010)

Defect evolution and diffusion mechanisms II : Fuccio Cristiano
Authors : N.E.B. Cowern
Affiliations : School of Electrical and Electronic Engineering, Newcastle University, UK

Resume : Germanium – well known as an important material option for high performance CMOS – has recently emerged as a remarkable test-bed for new concepts of defects and diffusion. Two years ago a study of B diffusion in Ge revealed the existence of a new class of mobile high-entropy defects [1]. Related to, but distinct from, a previous concept proposed by Seeger and Chik, the structure was proposed to be an amorphous pocket of nanoscale dimensions, or ‘morph’. This idea – and even the very existence of high-entropy mobile defects – has sparked disagreement [2]. Nevertheless, a detailed comparison of temperature-dependent data on radiation-enhanced diffusion of B and host atoms in Ge confirms that, in this system, interstitial-mediated diffusion mechanisms of B and especially host atoms at high temperature involve unusually high entropies (in the range of several tens of k). The talk shows how a surprising depth of detail can be obtained about the way the interacting defects evolve during self-diffusion and the microscopic process of displacement and migration of dopant atoms. These insights confirm the morph concept, placing it on a comparable footing with the better known compact point defects. Implications for other systems, including silicon, are discussed with reference to recent research reports. [1] N. E. B. Cowern, S. Simdyankin, C. Ahn, N. S. Bennett, J. P. Goss, J.-M. Hartmann, a. Pakfar, S. Hamm, J. Valentin, E. Napolitani, D. De Salvador, E. Bruno, and S. Mirabella, Phys. Rev. Lett. 110, 155501 (2013). [2] A. Chroneos and H. Bracht, Appl. Phys. Rev. 1, 011301 (2014)

III-V processing and devices II : Iain Thayne
Authors : L. Czornomaz, V. Djara, V. Deshpande, E. Uccelli, N. Daix, D. Caimi, C. Rossel, M. Sousa, H. Siegwart, C. Marchiori, and J. Fompeyrine
Affiliations : IBM Research GmbH Zürich Laboratory, Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland

Resume : The scaling of CMOS technology over the past four decades has revolutionized our society. The microelectronic industry is now facing some serious challenges in shrinking those dimensions beyond the 14nm node. Pure geometrical scaling does not bring anymore the expected benefits in terms of performance and power consumption. In the past decade, however, the industry gradually moved to innovation-driven scaling and brought to the market chips based on strained silicon, silicon-on-insulator, high-k/metal gate technology, tri-gate devices… This trend will continue with the move to high-mobility channel materials such as SiGe and III-V compound semiconductors that will need to be co-integrated on the same platform. Numerous challenges still have to be tackled in order to turn the high-mobility CMOS concept into an industrial solution. In this contribution, we will review how direct wafer bonding has enabled the integration of high-quality InGaAs-on-insulator on large-scale Si substrates [1,2,3]. Key process modules for the fabrication of CMOS-compatible self-aligned InGaAs MOSFETs will be addressed [4,5]. Finally, hybrid III-V/SiGe dual-channel CMOS inverters will be presented [6,7]. [1] L. Czornomaz et al., IEDM (2012), [2] N. Daix et al., APL Mat 2, 086104 (2014), [3] E. Uccelli et al., SSDM (2014), ), [4] L. Czornomaz, et al., ESSDERC (2013), [5] V. Djara et al., EuroSOI-ULIS (2015), [6] L. Czornomaz et al., IEDM (2013), [7] L. Czornomaz et al., SNW (2014)

Authors : John Buckeridge (1), C. Richard A. Catlow (1), Aron Walsh (2), David O. Scanlon (1), Alexey A. Sokol (1)
Affiliations : 1) University College London, Kathleen Lonsdale Materials Chemistry, Department of Chemistry, 20 Gordon Street, London WC1H 0AJ, United Kingdom; (2) Centre for Sustainable Chemical Technologies and Department of Chemistry, University of Bath, Claverton Down, Bath BA2 7AY, United Kingdom.

Resume : GaN is an important wide-gap semiconductor that is an essential component in blue light emitting diodes. Producing p-type layers has proven to be a major challenge, which has only been overcome by doping with large concentrations of Mg. Exactly how doping affects the minority charge carrier concentration remains a controversial issue, with many theoretical studies producing contradicting results. We present results of calculations based on a hybrid quantum mechanical/molecular mechanical embedded cluster approach to modelling defect formation associated with divalent metal dopants in GaN, with a particular focus on the technologically crucial case of Mg doping. As this approach gives a consistent description of polarisation and provides access to a well-defined reference, accurate and unambiguous defect levels are determined. From our calculations we show that isolated Mg atoms act as very deep traps for holes, which explains the lack of p-type activity in lightly doped samples. We attribute native n-type conductivity to N vacancies, which act as shallow donors. A large amount of experimentally determined optical data can be assigned to these N vacancies, which are charge-compensating defects for divalent dopant incorporation. Our calculated defect ionisation levels associated with the dopants are in excellent agreement with a wide range of experimental data.

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Authors : Luis A. Marqués, María Aboy, Manuel López, Iván Santos, Pedro López, Lourdes Pelaz
Affiliations : Departamento de Electrónica, ETSI de Telecomunicación, Universidad de Valladolid, Paseo de Belén 15, 47011 Valladolid, SPAIN

Resume : Modern techniques, such as ultra-fast laser annealing, have been proposed for the activation of ion implanted dopants (e.g. boron) in very thin layers near the silicon surface, without harming the underlying buried device layers, which is of critical importance for the fabrication of 3D integrated devices. These annealing treatments produce high temperatures and introduce stress in very localized regions of the substrate in the nanosecond regime. We have studied the early stages of self-interstitial clustering in silicon in such conditions of high temperature and stress using molecular dynamics simulation techniques. We have generated silicon samples of 200000 atoms where we introduced a 0.5% extra concentration of self-interstitials. Then samples were annealed at several temperatures and external pressures, both compressive and tensile. During the simulations we observed the formation of interstitial clusters with different atomic structures, ranging from spherical and amorphous-like clusters, to highly ordered extended configurations such as {311} defects, {111} rod-like defects and dislocation loops, and {100} planar defects. The particular morphology of formed interstitial clusters is found to be related to the applied external pressure and the annealing temperature, as it is observed in the experiments. From the molecular dynamics simulations we will analyze the atomic mechanisms leading to the formation of different defects.

Process and device modelling II : Ignacio Martin-Bragado
Authors : Christoph Zechner, Nikolas Zographos
Affiliations : Synopsys GmbH, Karl-Hammerschmidt-Strasse 34, 85609 Aschheim/Dornach, Germany; Synopsys Switzerland LLC, Thurgauerstrasse 40, 8050 Zurich, Switzerland

Resume : SiGe alloys are used in many types of electronic devices. For upcoming FinFET technologies, there is interest in the use of SiGe heterostructures in the complete molefraction range (0% - 100% Ge atoms). For high germanium molefraction and small device dimensions, inter-diffusion of Si and Ge atoms can lead to critical changes in the distribution of Si and Ge atoms, impacting channel strain and carrier mobility. A process model for Si-Ge interdiffusion has been developed which covers the needs for actual device fabrication processes. Interdiffusion is understood to be correlated with the diffusion of vacancies, interstitials, and dopant-defect pairs. We consider the impact of non-equilibrium point defect concentrations (such as interstitial super-saturation after ion implantation), the impact of compressive or tensile strain, and a twofold impact of doping: First, doping determines the local electron concentration and thereby the abundance of charged point defects, and second, the diffusion of dopant-defect pairs can contribute to the interdiffusion of Si and Ge atoms. The model covers the full range of possible Ge molefractions (0-100%). For undoped SiGe, it has been calibrated against a broad range of published experimental data for radio-tracer diffusion in SiGe and for interdiffusion in biaxially strained SiGe heterostructures grown on Si, stress-relaxed SiGe, or Ge. The extensions for doped SiGe are presented with a reference to few interdiffusion data for heavily doped SiGe heterostructures. Finally, the model has been consistently integrated into a set of models for the continuum process simulation of point defects and dopants in pure Si, SiGe, and pure Ge, in Sentaurus Process.

Authors : Oleg A. Mironov 1,2, and David R. Leadley 1
Affiliations : 1 Department of Physics, University of Warwick, Coventry, UK, 2 International Laboratory of High Magnetic Fields and Low Temperatures, Wroclaw, Poland

Resume : The extremely high 2DHG low temperature mobility of over 1.3*10^6 cm2/Vs (Ps=2.9?10^11 cm-2) [1-4] and very low hole effective mass (0.060 ± 0.001)mo determined from Shubnikov-de Haas oscillations has enabled the fractional quantum Hall effect (FQHE) to be observed for the first time in the ranges of magnetic fields up to 35T and temperatures 25mK

Authors : Ziyang Liu1,2, Clement Merckling1, Matty Caymax1, Rita Rooyackers1, Anabela Veloso1, Olivier Richard1, Hugo Bender1, Nadine Collaert1, Aaron Thean1, Wilfried Vandervorst1,2, Marc Heyns1,2
Affiliations : 1 imec, Kapeldreef 75, 3001, Leuven, Belgium; 2 KULeuven, Celestijnelaan, 3001, Leuven, Belgium;

Resume : Among all III-V nanowires (NWs), InAs NW is of great interest due to its high electron mobility and infrared bandgap. One of the main challenges for its application is to get controlled crystal phase in epitaxy, which entails the control of (111) planar defects (PDs) randomly distributed along the NW axial direction. For widely used vapor-liquid-solid (VLS) method, there were great progresses in PD control recently. Unfortunately, the VLS technique is not an optimum path for large scale NW device fabrication. Instead, selective area growth (SAG) is a method more desirable allowing placement control and avoiding metal impurities. But when using SAG, PD control is much more challenging. To our knowledge, InP NW is the only one that could be obtained in pure crystal phase by this method in the III-V NWs family till now. We report here the wurtzite (WZ) phase InAs NWs SAG on a patterned Si (111) substrate using a metal-organic vapor phase epitaxy (MOVPE) system. PD frequency in InAs NW is not influenced by NW diameter in our studied range (30-350nm), but can be controlled by basic growth parameters. WZ InAs NWs (hexagonality = 93%) with uniform diameter of about 220nm were obtained under the condition of high growth temperature, low V/III ratio and low growth rate. Because there is no liquid phase involved, this study also provides an important input to understand the mechanism of crystal phase switching during NW growth in a simple picture.

Authors : Enrico Napolitani (1), Ray Duffy (2), Nikolas Zographos (3), Mark van Dal (4)
Affiliations : (1) MATIS IMM-CNR, Department of Physics and Astronomy, University of Padova, Via Marzolo 8, Padova, Italy. (2) Tyndall National Institute, University College Cork, Lee Maltings, Dyke Parade, Cork, Ireland. (3) Synopsys Switzerland LLC, Thurgauerstr. 40, Zurich, Switzerland. (4) TSMC Europe BV, ATRD (Advanced Transistor Research Division), Kapeldreef 75, Leuven, Belgium.

Resume : Closing remarks


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Symposium organizers
Ray DUFFYTyndall National Institute / University College Cork

Lee Maltings, Dyke Parade - Cork T12 SRCP, Ireland

+353 21 234 6644
Enrico NAPOLITANIDipartimento di Fisica e Astronomia, Università di Padova and CNR-IMM

Via Marzolo 8, I-35131 Padova, Italy
Nikolas ZographosSynopsys Switzerland LLC

Thurgauerstr. 40 Zurich Switzerland

+ 41 44 567 1527
+ 41 44 567 1597
Mark van DalTSMC Europe BV / Logic Advanced Development Division (LADD)

Kapeldreef 75 Leuven Belgium

+ 32 16 28 8612