preview all symposia

Nanomaterials

I

Group-IV semiconductor materials for nanoelectronics and cryogenic electronics

Group-IV semiconductors, namely Si, Ge, Sn and their compounds, are the most important materials in micro- and nanoelectronics but they will also play a key role in future quantum devices. This symposium aims to share the latest research in the field of group-IV nanoelectronic materials and devices.

Scope:

Silicon (Si) is one of the most dominant semiconductor materials with versatile applications ranging from electronics over photovoltaics to sensors and actuators. Due to its intrinsically higher electron and hole mobility germanium (Ge) or silicon-germanium (SiGe) are rapidly gaining interest in micro- and nanoelectronics. The same holds true for tin (Sn) and its alloys with the other group-IV semiconductors (e.g., GeSn).

In nowadays nanoelectronics research with device dimensions approaching the single-digit-nanometer scale nanowires are often the building blocks of transistors. However, many processing methods and device concepts have to be adopted since nanostructures are generically subject to nano-size and quantum effects. These effects involve for instance quantum confinement, dielectric confinement, detrimental surface states, statistical issues of doping ultrasmall volumes, etc. This bears the risk to deteriorate the performance and reliability or even cause complete failure of the transistors. On the other hand, if fully understood, nano-size and quantum effects may open up new vistas for increased performance, reduced power consumption or even routes towards quantum computing.

Generally, nanostructures have a high surface-to-volume ratio and their properties are often dominated by the surface. Therefore, an increased understanding of the physical and chemical properties of group-IV semiconductor nanostructure interfaces to metals and dielectrics is mandatory to control and optimize gate control, threshold voltage, ohmic contacts, carrier transport, etc.

Finally, simulations and modelling are crucial for nanoelectronics, starting from ab-initio methods to model physical/quantum-chemical properties of group-IV nanostructures to device simulations modelling transport and performance.

Hot topics to be covered by the symposium:

  • Group-IV semiconductors (Si, Ge, Sn) and their mixtures/alloys for nanoelectronics
  • Fabrication, functionalization, doping, defect engineering of group-IV semiconductor nanostructures
  • Advanced contacts and dielectrics for group-IV nanoelectronics
  • Emerging device concepts (gate-all-around GAA-FETs, junctionless JL-FETs, steep-subthreshold slope FETs, functionality enhanced FETs, etc.)
  • Characterization and metrology of group-IV nanostructures and nanoelectronic devices
  • Simulations and modelling of fundamental properties and devices
  • Integration of 2D-materials with group-IV semiconductor nanostructures
  • Group-IV semiconductor devices towards quantum computing (solid state spin qubits)
  • Cryogenic electronics
  • Sensing applications

Confirmed list of invited speakers:

  • Ádám Gali (Wigner Research Centre for Physics, Budapest, Hungary)
  • Athanasios Dimoulas (NCSR Demokritos, Athens, Greece)
  • Enrico Napolitani (University of Padova, Italy)
  • Fernando Gonzalez-Zalba (Quantum Motion, UK)
  • Georgios Katsaros (IST, Klosterneuburg, Austria)
  • Jens Trommer (NaMLab, Dresden, Germany)
  • Joachim Knoch (RWTH Aachen, Germany)
  • Maksym Myronov (University of Warwick, UK)
  • Moritz Brehm (JKU University Linz, Austria)
  • Nic Chiang (TSMC, Taiwan)
  • Raffaella Calarco (CNR-IMM, Rome, Italy)
  • Thomas Ernst (CEA LETI, France)
  • Yordan Georgiev (HZDR, Germany)

Scientific committee members:

  • Birger Berghoff (RWTH Aachen, Germany)
  • Cristina Medina-Bailon (University of Granada, Spain)
  • Dirk König (ANU, Canberra, Australia)
  • Josef Weinbub (TU Wien, Austria)
  • Lado Filipovic (TU Wien, Austria)
  • Nikolay Petkov (Munster Technological University, Ireland)
  • Masiar Sistani (TU Wien, Austria)
  • Steffen Strehle (TU Ilmenau, Germany)
  • Viktor Svredlov (TU Wien, Austria)

Publications:

Attendees of Symposium I are invited to submit a paper to a Special Issue of Wiley’s physica status solidi (a).

Start atSubject View AllNum.Add
 
Silicon Nanowire Electronics : Daniel Hiller
14:00
Authors : T. Ernst, T. Dubreuil, S. Barraud
Affiliations : CEA-Leti, Université Grenobles Alpes, F-38000 Grenoble, France

Resume : 3D top down CMOS nanowire and nanosheet technologies have been studied for more than fifteen years and are now developed in industry for 3nm node. 3D stacked nanosheets GAA MOSFET devices will likely succeed to FinFET technology to offer higher performance with a greater design flexibility. In this work, such devices are successfully fabricated using a replacement high-k metal gate process and self-aligned contacts. Specific steps are introduced compared to a Finfet process including epitaxy, selective etch process, replacement metal gate and self-aligned contacts to enable 3D stacked nanowires or nanosheet transistors. The 3D configuration introduced some parasitic capacitive and resistive effects that limits for instance the number of stacked channels for an optimum performance. SPICE simulations of RO based on a revised version of L-NSP model calibrated on our experimental results show an optimal energy efficiency for GAA structures integrating up to 3 stacked Si channels We will also discuss specific effects introduced by nanowire geometry compared to 2D thin Si film: quantization effects, mobility and transport. Finally, we will describe how the benefit of vertically stacked-channels can be exploited for the development of novel 3D 1T1R RRAM architecture combining both emerging devices (GAA and RRAM). Thanks to a proper connection of SourceLines (SLs), BitLines (BLs), and WordLines (WLs), we propose to implement a memory-centric hyperdimensional computing (HDC) algorithm for language recognition with a high degree of parallelism. Our simulations validate the main HD vector operations (i.e generation of seed hypervectors, XNOR, SHIFT, etc.) with an efficiency reaching up to 95%. On this basis, we demonstrated a first experimental implementation of AND operation with a 1kb RRAM array. [1] T. Ernst et al., IEEE Int. Electron Dev. Meeting (IEDM) 2006 [2] S. Barraud et al., IEEE Int. Electron Dev. Meeting (IEDM) 2017 [3] S. Barraud et al. IEEE Int. Electron Dev. Meeting (IEDM) 2018 [4] S. Barraud et al IEEE Int. Electron Dev. Meeting (IEDM) 2020 [5] T. Dubreuil et al., IEEE Int. Memory Workshop (IMW) 2022

I.1.1
14:30
Authors : Giulio Galderisi [1]; Thomas Mikolajick [1,2]; Jens Trommer [1]
Affiliations : [1] Nanoelectronic Materials Laboratory (NaMLab), Nöthnitzer Str. 64a, 01187 Dresden, Germany; [2] Chair for Nanoelectronics, TU Dresden, Nöthnitzer Str. 64, 01187 Dresden, Germany

Resume : Due to the ubiquity of electronic circuits and systems in today’s interconnected world, operating a given device in the broadest possible temperature range acquires significant importance. The possibility of fabricating devices that can be employed in several temperature hostile environments using the same technology can drastically improve the energy efficiency of the electronic systems and simplify the overall production chain. This is even more true in the case of CMOS-compatible technologies. The chance to realize circuits that can efficiently function at both low/cryogenic temperatures for quantum-readout or aerospace applications, and at high temperatures, for automotive and power electronics is incredibly appealing. Due to their doping-free channels, Schottky barrier transistors are assumed to be intrinsically more robust against temperature-induced degradation effects at both extremes, such as dopants freeze-out or dominant source-drain leakage. Among them, reconfigurable field-effect transistors (RFETs) with multiple independent gates are especially interesting for designing circuits due to their polarity control features, meaning that the transistor can be operated with unipolar n-type and p-type characteristics on demand. This way, different circuit functionalities can be mapped onto the same physical structure. The additional gate electrodes can be used to tune transistor characteristics, like off-state leakage or threshold voltage, to match the circuit performance to the design target. In this work, we present insights into the temperature-dependent characteristics of silicon- and germanium-based devices for a broad temperature range, discussing the effects of the temperature environment on the transistor’s transport physics.

I.1.2
15:00
Authors : Lukas Wind [1], Masiar Sistani [1], Özgür Demirkiran [1], Raphael Böckle [1], Peter Schweizer [2], Xavier Maeder [2], Johann Michler [2], Walter M. Weber [1]
Affiliations : [1] Institute of Solid State Electronics, TU Wien, Vienna, Austria; [2] Laboratory for Mechanics of Materials and Nanostructures, EMPA, Thun, Switzerland;

Resume : High-quality electrical contacts are of utmost importance for nanoscale Si devices as they have a large impact on their electrical performance, reliability and reproducibility. Furthermore, as the CMOS scaling is about to approach fundamental physical limits, new device concepts are needed to further increase the functionality of electronic systems. In this regard, we show a novel thermally induced Al-Si exchange reaction process. Thereto, we fabricated Si nanowires and nanosheets from fully-depleted SOI by top down means and used these to form monolithic Al-Si heterostructures. [1] In contrast to their bulk counterpart, abrupt and void-free metal-semiconductor interfaces are formed, providing well-defined and reproducible Schottky junctions. The selective and controllable transformation of Si nanostructures into Al provides pure and single-crystalline Al-leads, revealing resistivities as low as ρ = (6.31 ± 1.17) × 10^–8 Ω m and breakdown current densities of Jmax = (1 ± 0.13) × 10^12 Ω m^–2. Importantly, during the Al−Si contact formation no intermetallic phases are formed, overcoming the difficulty of complex growth kinetics of state-of-the-art metal silicides and reducing process variability and yield issues. Structural TEM and EDX analysis confirmed the void-free and abrupt Al−Si heterojunction properties. To assess the electrical performance, Al-Si heterostructures were implemented within an insulator shell into a device architecture having three independent omega-shaped top-gates. The resulting reconfigurable filed-effect transistors (RFET) are capable of dynamically switching between p- and n-type operation even during runtime. Detailed and systematic electrical characterizations of the Al-Si system revealed highly symmetric effective Schottky barriers for electrons and holes system, also leading to symmetric on/off currents and threshold voltages for both operation modes. This is of utmost importance to fully exploit the advantages of RFETs on a complementary circuits level. To demonstrate the functional diversity of the proposed device platform, additional gates were added to the RFET structure, to yield wired-AND gate functions within a single transistor. The Al-Si technology platform enables a simple implementation of dynamically reconfigurable logic gates, allowing e.g. switching between NAND to NOR functions. Thus, in more complex logic circuits, RFETs are considered a powerful concept to reduce the transistor count and critical paths, paving the way to lower footprint and increased energy efficient devices. Exploiting the Al-Si junction reproducibility, we further demonstrate RFETs based on parallel arrays of Al-Si-Al heterostructures, enabling drive-current upscaling. [1] L. Wind, et al. ACS Appl. Mater. Interf. 2022, DOI: 10.1021/acsami.2c04599

I.1.3
15:15
Authors : Hamilton Carrillo-Nuñez, Cristina Medina-Bailon Vihar Georgiev and Asen Asenov
Affiliations : University of Glasgow

Resume : One of the most popular qubit architectures is the silicon (Si) spin qubit, which relies on the physics of Si dopants and electrostatic quantum dots made. One of the main challenges faced in the quantum computing is to estimate the interaction (entanglement) between the spin qubits and the decoherence. Such characteristic could be estimated from the measurements but the best way to understand the underlying physics which is determining the interaction between the qubits is archived by quantum mechanical simulations. For this reason, in this paper, we report full-band quantum transport simulation of a p-type silicon nanowire transistors with two gates and two single dopants under each gate. Each dopant represents a Si spin qubit and to simulate the interaction between the qubits we have developed and implemented a mode-space-based full-band quantum transport simulator with phonon scattering using the six-band k·p method. Based on the non-equilibrium Green’s function formalism and self-consistent Born’s approximation, an expression for the hole-phonon interaction self-energy within the mode-space representation is introduced. The methodology is implemented in our in-house code called Nano-Electronic Simulation Software (NESS). We efficiently simulated a transistor like device, which may be relevant for silicon spin qubit quantum technologies, formed by two GAA in series and a p-type Si nanowire channel with a single dopant within each gated region. Also, our findings suggest that hole-phonon interactions have a significant detrimental impact on the transistor performance when compared to ballistic simulations.

I.1.4
15:30 Coffee Break    
 
Cryo Electronics : Vihar Georgiev
16:00
Authors : Joachim Knoch
Affiliations : Chair of Semiconductor Electronics and Institute of Semiconductor Electronics, RWTH Aachen University, Sommerfeldstraße 18, 52074 Aachen

Resume : Silicon-based spin qubits are attracting significant attention for up-scaling of quantum information processors. Reasons for this are the large coherence times (in particular in isotopically purified 28Si) and the ability to manufacture them with the highly mature Si-CMOS technology which facilitates co-integration of cryogenic control electronics (cCMOS) in a straightforward way. However, cCMOS circuits need to be operated at very low operating voltages. This in turn asks for a very steep switching behavior with very small inverse subthreshold slopes SS. While ideal MOSFET theory suggests that the required small SS are achievable at liquid helium temperatures, experimentally, SS usually saturates at SS values of approximately 15 mV/dec. Moreover, SS increases substantially for gate voltages close tot he threshold voltage. The latter phenomenon is called inflection. The saturation of SS stems from an exponentially decaying density of delocalized (current carrying) states at the band edges called band-tailing which is due to disorder (defects, micro [1]roughness etc.); inflection occurs because of an additional Gaussian-distributed density of localized interface states that reduces the gate impact. Furthermore, random dopant effects in nanoscale FETs become more pronounced yielding Coulomb oscillations in the case of the required small bias voltages. As a result, modifications in the device layout are necessary in order to realize optimized steep slope cryogenic field-effect t

I.2.1
16:30
Authors : Hung-Li Chiang, Iuliana Radu
Affiliations : Corporate Research, Taiwan Semiconductor Manufacturing Company

Resume : The state-of-the-art CMOS technologies already offer the best power-performance levels available today. However, CMOS power efficiency is limited by the supply voltage (VDD) which cannot be scaled much below 0.75V due to threshold voltage (VTH) and leakage constraints. Recently, cryogenic CMOS (cryo-CMOS) receives renewed interest, as a promising candidate for High-Performance Computing (HPC) applications in data centers and for control electronics to support quantum computing. It provides a chance to obtain higher performance or power reduction by offering a reliable way for a steeper subthreshold slope (SS) at lower operating temperatures. With the centering leakage current to the level at room temperature, steepened SS at cryogenic conditions enables VTH and VDD scaling, while VTH adjustments are requisite to achieves the benefits mentioned above. In this talk, we will introduce the proposed transistors for cryogenic operations and the method for VTH adjustments, including band-edge work-function metals with the dipole layers in the gate stacks and channel materials with lower bandgaps. By exploring new materials for cryo-CMOS, other benefits, including higher mobility, metal lines with lower resistance, and enhanced reliability, will be also presented to further enhance the performance of cryo-CMOS.

I.2.2
17:00
Authors : Masiar Sistani[1], Raphael Böckle[1], Alois Lugstein[1], Walter M. Weber[1] Minh Anh Luong[2], Martien I. den Hertog[2]
Affiliations : [1] Institute of Solid State Electronics, TU Wien, Vienna, Austria [2] Institut Néel, CNRS, Grenoble, France

Resume : Information and communication technology has become ubiquitous in everyday life. Emerging distributed computing paradigms such as the “Internet of Things” are demanding the implementation of novel electronic device functionalities that go beyond the capabilities of conventional field effect transistors (FETs). In this context, nanoscale Ge departs from its bulk counterpart and delivers unique electronic properties. Thereto, a highly interesting transport mechanism is the transferred electron effect, enabling negative differential resistance (NDR). Here, we exploit the nanometer scale properties of Ge nanowires with unique monocrystalline Al contacts to deliver a strong and reproducible NDR even at room temperature. Based on the characterization at room- and cryogenic temperatures, we have analyzed the NDR effect in Al-Ge-Al NW heterostructures embedded in FET architectures for photonic- and nanoelectronics applications. In this respect, we further combine the advantage of Ge covering the C-band optical communication range and the nanocylinder resonator shape of NWs to demonstrate a photodetector with switchable photo-conductance, effective dark-current suppression and remarkably high polarization sensitivity.[1] This highly versatile Ge photodetector platform may pave the way for innovative optoelectronic devices including compact light tunable memories, or light effect transistors. Investigating applications beyond the static capabilities of conventional CMOS architectures, the proposed Al-Ge-Al NW heterostructures were embedded into a three-gate FET architecture to deliver effective charge carrier polarity control enabling distinct programmable NDR at runtime.[2] This so called NDR-mode RFET provides a unique fusion of the concept of reconfiguration and NDR embedded in a universal adaptive transistor that may enable energy efficient programmable circuits with multi-valued operability that are inherent components of artificial intelligence electronics. [1] M. Sistani, R. Böckle, M. G. Bartmann, A. Lugstein, W. M. Weber, ACS Photonics 2021, 8, 3469. [2] M. Sistani, R. Böckle, D. Falkensteiner, M. A. Luong, M. I. den Hertog, A. Lugstein, W. M. Weber, ACS Nano 2021, 15, 18135.

I.2.3
Start atSubject View AllNum.Add
 
Group-IV Quantum Dots : Ray Duffy
09:00
Authors : Daniel Jirovec (1), Andrea Hofmann (1), Andrea Ballabio (2), Philipp M. Mutter (3), Giulio Tavani (2), Marc Botifoll (4), Alessandro Crippa (1), Josip Kukucka (1), Oliver Sagi (1), Frederico Martins (1), Jaime Saez-Mollejo (1), Ivan Prieto (1), Maksim Borovkov (1), Marek Rychetsky (5), David. L. Craig (5), Natalia Ares (6), Jordi Arbiol (4,7), Guido Burkard (3), Daniel Chrastina (2), Giovanni Isella (2), Georgios Katsaros (1)
Affiliations : 1. Institute of Science and Technology Austria, Am Campus 1, 3400 Klosterneuburg, Austria 2. L-NESS, Physics Department, Politecnico di Milano, via Anzani 42, 22100 Como, Italy 3. Department of Physics, University of Konstanz, D-78457 Konstanz, Germany 4. Catalan Institute of Nanoscience and Nanotechnology (ICN2), CSIC and BIST, Campus UAB Bellaterra, Barcelona, Catalonia, Spain 5. Department of Materials, University of Oxford, Parks Road, Oxford OX1 3PH, United Kingdom 6. Department of Engineering Science, University of Oxford, Parks Road, Oxford OX1 3PJ, United Kingdom 7. ICREA, Passeig de Lluis Companys 23, 08010 Barcelona, Catalonia, Spain

Resume : Spin qubits are considered to be among the most promising candidates for building a quantum processor [1]. While most of the works on spin qubits have focused on electrons, the interest in holes as potential spin qubits has strongly increased in the past few years. Ge hole spin qubits, in particular, have moved into the focus of interest due to the ease of operation and compatibility with Si technology [2]. In addition, Ge offers the option for monolithic superconductor-semiconductor integration. From 2018 and within just three years a Loss-DiVincenzo (LD) [3], two-qubit gate devices [4] and a four-qubit Ge quantum processor [5] have been realized demonstrating the potential of Ge for quantum information. Here I will present a hole spin qubit operating at fields below 10mT, the critical field of Al, by exploiting the large out-of-plane hole g-factors in planar Ge and by encoding the qubit into the singlet-triplet states of a double quantum dot [6]. We observe electrically controlled g-factor-difference-driven rotations reaching 600 MHz and dephasing times of 1µs which we extend beyond 150µs with echo techniques. By varying the magnetic field direction we can furthermore investigate the hole spin orbit physics [7]. By performing Landau-Zener sweeps we can disentangle the Zeeman mixing effect from the cubic Rashba spin-orbit induced coupling between singlet and triplet states. Our results emphasize the need for a complete knowledge of the energy landscape when working with hole spin orbit qubits with large g-factor differences and demonstrate that Ge hole singlet-triplet qubits are competing with state-of-the art GaAs and Si singlet-triplet qubits but they can be operated at much lower fields underlining their potential for on chip integration with superconducting technologies. References: [1] G. Burkard, T. D. Ladd, A. Pan, J. M. Nichol, J. R. Petta, arXiv: arXiv:2112.08863v1 (2021) [2] G., Scappucci, C. Kloeffel, F. A. Zwanenburg et al., Nat. Rev. Mater. 6, 926 (2021) [3] H. Watzinger, J. Kukučka, L. Vukušić, F. Gao, T. Wang, F. Schäffler, J.-J. Zhang, G. Katsaros, A Ge hole spin qubit, Nature Communications 9, 3902 (2018). [4] N. W. Hendrickx, D. P. Franke, A. Sammak, G. Scappucci, M. Veldhorst, Nature 577, 487-491 (2020). [5] N. W. Hendrickx, W. I. L. Lawrie, M. Russ, F. van Riggelen, S. L. de Snoo, R. N. Schouten, A. Sammak, G. Scappucci, M. Veldhorst, A four-qubit germanium quantum processor, Nature 591, 580-585 (2021). [6] D. Jirovec, A. Hofmann, A. Ballabio, et al., Nat. Mater., 2021, 20, 1106. [7] D. Jirovec et al., Phys. Rev. Lett. 128, 126803 (2022).

I.3.1
09:30
Authors : Jonathan G.C. Veinot
Affiliations : Department of Chemistry, University of Alberta, Edmonton, Alberta T6G 2G2, Canada

Resume : ‘Silicon nanocrystals (SiNCs)’ exhibit optoelectronic and chemical characteristics that make them particularly attractive as active materials in photovoltaic cells, luminescent solar concentrators, LEDs, battery anodes, as well as a variety of therapeutic and imaging modalities. Because SiNCs are biocompatible and toxic-metal-free, they also provide a convenient circumvention of legislation that limits use of status quo metal-based quantum dots in consumer products. Not surprisingly, nanoparticle internal structure influences optical, chemical and material properties and it is essential to elucidate the NC core structure if they are to realize their full potential. By applying a diverse array of complementary techniques including 29Si solid-state NMR, FTIR, XPS, XRD, and TEM to the characterization of monodisperse hydride-terminated SiNCs (H-NCs; d = 3 to 64 nm) we have discovered they exhibit size dependent layered structures consisting of surface, subsurface and core silicon species. This presentation will include a detailed discussion of our investigation and outline the potential impact of these structural features on the widespread deployment of SiNCs in applications noted above.

I.3.2
09:45
Authors : K.-H. Heinig1, J. von Borany1, H.-J. Engelmann1, G. Hlawacek1, R. Hübner1, F. Klüpfel3, W. Möller1, M.-L. Pourteau2, G. Rademaker2, M. Rommel3, L. Baier3, P. Pichler3, R. Tiron2
Affiliations : 1 Helmholtz-Zentrum Dresden-Rossendorf (HZDR), D-01328 Dresden, Germany; 2 Univ. Grenoble Alpes, CEA, LETI, F-38000 Grenoble, France; 3 Fraunhofer Institute for Integrated Systems and Device Technology (IISB), D-91058 Erlangen, Germany

Resume : Low-power logic and memory circuits remain a main task for the next generations of energy-efficient electronic devices. Single Electron Transistors (SETs) are extremely low energy dissipation devices. However, SETs operate usually at cryogenic temperatures and have some serious drawbacks. Fortunately, Field Effect Transistors (FETs) and SETs are complementary: The SET is the champion of low-power consumption while FETs advantages, like high-speed, driving, voltage gain and input impedance can compensate exactly for SET's intrinsic drawbacks. To overcome the drawback of cryogenic temperature operation, each SET has to be manufactured with a quantum dot of a size of just a few nanometers, and this dot has to be located not more than about one nanometer apart from the electrodes. The large-scale implementation of SETs in room-temperature electronics is hampered by its unresolved manufacturability because such requirements are beyond the limits of present lithography. We employed self-organization to overcome the present-day limits of lithography. On 5…8nm thick SiO2 layers of (001)Si wafers about 30nm thick a-Si layers have been deposited and subsequently irradiated with 50 keV Si+ ions. The irradiation leads to ion beam mixing at the upper and lower Si/SiO2 interfaces and transforms the buried SiO2 layer to SiOx with x~1. Then, pillar arrays have been fabricated from such layer stacks using electron beam lithography and plasma etching. Arrays of pillars with different diameters from 100nm down to less than 20nm have been produced, where the smallest pillar diameters have been further reduced to ~10nm by plasma oxidation and selective oxide etching (sacrificial oxidation). In this manner we manufactured SiOx disks of ~10nm diameter and 5nm thickness sandwiched between the Si of the pillars. During Rapid Thermal Processing (RTP) of such pillars at 1050°C for 60s, phase separation SiOx  (1-x/2)Si + x/2SiO2 occurs via formation of Si nuclei and Ostwald ripening. Close to the SiO2/Si interfaces the Si excess of SiOx condensates on the upper/lower Si of the pillar, i.e. no Si nuclei can form there. The nucleation rate at the rim of the disk is reduced too, especially if there are traces of oxygen in the ambient. Thus, in nanopillars of ~10nm diameter a single Si dot of ~3nm forms in the ~5nm thick SiO2 disk, whereas in thicker pillars a few dots are found. From such nanopillars vertical nanowire Gate-All-Around SETs (nw GAA-SETs) are fabricated by gate oxide formation using plasma oxidation and gate layer deposition followed by contact formation. The nw GAA-SETs can be combined with nw GAA FETs to fabricate integrated hybrid SET/FET devices, where the FETs are responsible for current amplification. The funding from the European Union’s Horizon 2020 research and innovation program under grand agreement Nº 688072 (project acronym: Ions4SET) is gratefully acknowledged.

I.3.3
10:00
Authors : F. Honeit, R. Hübner, C. Röder, J. Beyer, J. Heitmann
Affiliations : Institute of Applied Physics, TU Bergakademie Freiberg, Leipziger Str. 23, 09599 Freiberg, Germany; Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum Dresden-Rossendorf, 01314 Dresden, Germany;

Resume : Ge nanocrystals embedded in amorphous TaZrOx matrices were synthesized by a magnetron co-sputtering process in a size-controlled manner, separated from each other by a superlattice approach of alternating TaZrOx-Ge/TaZrOx layers. Ge offers, in contrast to silicon, a large Exciton-Bohr radius, which allows the regulation of the bandgap by the diameter. After annealing at 725°C, Ge nanostructures were found to phase-separate and crystallize [1]. The addition of Sn to Ge promises a way towards a direct bandgap Ge-based semiconductor material [2] in a wide concentration range between 6 at.-% and 22 at.-% of Sn [3]. A direct bandgap material, which is fully compatible to common Si-CMOS processes would enable the integration in future devices, like light emitters or detectors. The fabrication of GeSn alloys is challenging, due to the low solubility of Sn in Ge [4] but it is known that Ge nanocrystals after annealing contain a higher concentration of foreign atoms than expected in thermodynamic equilibrium [1]. Different structural measurements like EDX or Raman scattering monitor the structural changes within the Ge nanostructures by addition of Sn to the superlattice structure under annealing temperatures between 600 °C and 800 °C. TEM EDX measurements revealed that the TaZrOx, which acts as an efficient diffusion barrier for Ge, does not prohibit the diffusion of the Sn completely. However, the formation of pure Sn nanocrystals was not observed. In addition, crystallization of the matrix material can be avoided for appropriate annealing temperatures. [1] D. Lehninger, F. Honeit, D. Rafaja, V. Klemm, C. Röder, L. Khomenkova, F. Schneider, J. von Borany, and J. Heitmann, MRS Bull. 511–512, 654 (2022). [2] A. Slav, C. Palade, C. Logofatu, I. Dascalescu, A. M. Lepadatu, I. Stavarache, F. Comanescu, S. Iftimie, S. Antohe, S. Lazanu, V. S. Teodorescu, D. Buca, M. L. Ciurea, M. Braic, and T. Stoica, ACS Appl. Nano Mater. 2, 3626 (2019). [3] W.-J. Yin, X.-G. Gong, and S.-H. Wei, Phys. Rev. B 78, 161203(4) (2008). [4] H. Li, J. Brouillet, A. Salas, X. Wang, and J. Liu, Opt. Mater. Express 3, 1385 (2013).

I.3.4
10:15
Authors : Maren Dworschak, Niklas Kohlmann, Martin Müller, Lorenz Kienle, Jan Benedikt
Affiliations : Institute of Experimental and Applied Physics, Experimental Plasma Physics, Kiel University, Germany; Institute of Material Science, Synthesis and Real Structure, Kiel University, Germany; Institute of Physics, Czech Academy of Sciences, Prague, Czech Republic; Institute of Material Science, Synthesis and Real Structure, Kiel University, Germany; Institute of Experimental and Applied Physics, Experimental Plasma Physics, Kiel University, Germany;

Resume : The HelixJet, a plasma source operating under atmospheric pressure with RF power, was used for the synthesis of silicon nanoparticles (Si-NP) in context of relevance in nanomedicine, sensor technology and nanotechnology. The synthesized particles have been analyzed in regard to their size, crystallinity, structure and photoluminescence. Distinct varieties of nanomaterials could be synthesized depending on the operation parameters of the HelixJet. In-flight annealing post synthesis allows the formation of large crystalline nanoparticles with diameters up to 200 nanometers. These large crystals can be used in all-dielectric nanophotonics. In addition, metals such as manganese could be incorporated into the nanocrystals creating silicides (e.g. manganese silicides). Higher manganese silicides show ferromagnetic behavior which makes them ferromagnetic semiconductors suitable for opto-electronic applications. Different approaches to modify the surface passivation of the generated nanocrystals will be presented here.

I.3.5
10:30 Coffee Break    
 
Group-IV Epitaxial Materials : Walter Weber
11:00
Authors : Moritz Brehm
Affiliations : Johannes Kepler University Linz, Austria

Resume : The realization of next-generation nanoelectronic and optoelectronic Si-based device ideas is currently hindered by the limited critical thickness of strained, pseudomorphic, and Ge-rich SiGe layers grown on Si(001) substrates, i.e., before their elastic or plastic relaxation. Some of these applications include novel nanoelectronic devices based on robust planar flat-film technology, such as hole-gas field-effect transistors, Josephson field-effect transistors, and negative differential resistance devices. In photonics and optoelectronics, the realization of thick but pseudomorphic and Ge-rich SiGe films could enable the implementation of double heterostructures to advance the present, fully-Group-IV-based room temperature light-emitting devices or photodetectors. However, for many of these applications, the Ge concentrations for the thick but pseudomorphic SiGe films (TPF) should ideally be in the range between 50% and 100%. Such Ge concentrations would ensure, e.g., large enough band offsets between the Si and SiGe layers. Yet, literature reports mainly focus on TPFs with low Ge contents smaller than 50%, with only a few exceptions for which the critical thickness for pronounced relaxation was evaluated for single Ge concentrations of about 55%. This work investigates how far we can supersaturate the thickness of SiGe/Si layers before a pronounced relaxation of the TPFs for Ge concentrations ranging from ~36% to 100% and film thicknesses from ~1 nm to ~16 nm. We compare our results to the theoretical values of the critical thickness of relaxation proposed by People and Bean while no other experimental data is present for this range of alloys. By employing solid-source MBE-growth of TPFs at unconventionally low growth temperature, we can achieve an excellent root-mean-square surface roughness of < 0.2 nm, even if the layer thickness exceeds the theoretical values by ~60%. Furthermore, we show that for obtaining Ge rich SiGe layers with excellent surface roughness and film thickness while maintaining excellent structural and optical properties, epitaxy has to be performed at growth temperatures at least as low as T = 350°C. Additionally, we demonstrate that these TPFs can be implemented in nanoelectronic and optoelectronic devices. Group-IV double-heterostructure diodes that contain TPF show persistent light emission in a wide temperature window from 10 K to 360 K (90°C).

I.4.1
11:30
Authors : Eugenio Zallo, Raffaella Calarco
Affiliations : Eugenio Zallo 1 - Paul-Drude-Institut für Festkörperelektronik, Leibniz-Institut im Forschungsverbund Berlin e.V., Hausvogteiplatz 5-7, 10117 Berlin, Germany 2 - Walter-Schottky-Institut and Physik Department, Technische Universität München, Am Coulombwall 4, 85748 Garching, Germany ; Raffaella Calarco 1 - Paul-Drude-Institut für Festkörperelektronik, Leibniz-Institut im Forschungsverbund Berlin e.V., Hausvogteiplatz 5-7, 10117 Berlin, Germany 3 - Istituto per la Microelettronica e Microsistemi (IMM), Consiglio Nazionale delle Ricerche (CNR), Via del Fosso del Cavaliere 100, 00133, Rome, Italy

Resume : The ability of growing high-quality epitaxial films of conventional (e.g. silicon and III-Vs) crystalline materials forms the basis for the development of semiconductor technology. Recently, two-dimensional (2D) materials have attracted increasing interest in material science due to their extraordinary properties such as efficient light-matter coupling, miniaturization capabilities and excellent tunability [1]. However, the epitaxial growth of large-scale and high-crystalline-quality van der Waals (vdW) materials remains an urgent challenge for the realization of novel devices technologies. In this talk, the vdW epitaxy of Ge-Sb-Te (GST) alloys on Si(111) will be presented [2,3]. These are compounds employed in non-volatile random-access memory and rewriteable optical storage media thanks to the rapid and reversible transformation between the amorphous and crystalline states and consist of lamellae separated by vdW gaps in the ordered crystalline phase. We report a methodology for the study of the 2D character of epitaxial GST by looking at the weak inter-lamellae interactions. Our unique approach is the use of molecular beam epitaxy for the controlled synthesis of ultrathin films combined with Raman spectroscopy for the investigation of the PCM properties. The shift of the vibrational modes in the low-frequency range results in a direct probe of the film thickness [4]. Moreover, the role of surface interaction between 2D layered materials and substrate surface is predicted by choosing low-lattice matched InAs(111) substrates prepared into self- and un-passivated surfaces, and the formation of ordered and disordered GST phases allows to directly infer the nature of the epitaxy [5]. These results pave the way for mastering and design of vdW epitaxial growth of 2D heterostructures as well as hybrid 2D and non-layered materials. Finally, we present a cutting edge UHV cluster tool for the synthesis of ultrapure 2D materials and their heterostructures. The system consists of an MBE connected via automated UHV transfer channel to an analytical chamber with capabilities for in-situ optical confocal spectroscopy (photoluminescence and Raman) at lattice temperatures 300K to ~10K. We describe the materials families that the system can synthesize and explore potential directions. [1] A. K. Geim, and I. V. Grigorieva, Nature 499 (2013) 419. [2] V. Bragaglia, F. Arciprete, W. Zhang, A. M. Mio, E. Zallo, K. Perumal, A. Giussani, S. Cecchi, J. E. Boschker, H. Riechert, S. Privitera, E. Rimini, R. Mazzarello, and R. Calarco, Sci. Rep. 6 (2016) 23843. [3] E. Zallo, S. Cecchi, J. E. Boschker, A. M. Mio, F. Arciprete, S. Privitera, and R. Calarco, Sci. Rep. 7 (2017) 1466. [4] E. Zallo, D. Dragoni, Y. Zaytseva, S. Cecchi, N. I. Borgardt, M. Bernasconi, and R. Calarco, Phys. Status Solidi (RRL) (2020) 2000434. [5] F. Arciprete, J. E. Boschker, S. Cecchi, E. Zallo, V. Bragaglia, and R. Calarco, Adv. Mater. Inter. 9 (2022) 2101556.

I.4.2
12:00
Authors : Maksym Myronov
Affiliations : Department of Physics, The University of Warwick, Coventry CV4 7AL, UK

Resume : Semiconductors have had a monumental impact on our society. They power the modern world and enable the systems and products that we use to work, communicate, travel, entertain, harness energy, treat illness, make new scientific discoveries, and much more. Semiconductor materials are the foundation of modern electronics including phones, computers and many other gadgets and devices. Anything that is computerized or uses radio waves contains semiconductor devices. Therefore, the semiconductor industry is one of the largest industries in the world and has grown to be a $555 billion industry in 2021. This being a result of the essential role semiconductors have come to play as the backbone of all solid-state electronic, optoelectronic and sensor devices. In the foundation of all devices are epiwafers, which are manufactured using epitaxy or an epitaxial growth process. The underlying crystal is called a wafer or substrate, and is what determines the orientation of any subsequently grown over layers, called epitaxial layers or epilayers. The final wafer-epilayer structure is then referred to as an epiwafer. Over 99% of all semiconductor devices are fabricated of or on silicon (Si). Because it is cheap material with superior properties, manufacturable and multifunctional. Novel group IV semiconductor epitaxial structures created of Si, Germanium, Carbon and Diamond or Tin materials on a Si or Si on Insulator (SOI) wafers are a natural evolution in improvement of properties of modern state of the art Si devices and expanding their existing functionalities. They underpin application of these materials with new or enhanced properties in electronic, photonic, photovoltaic, thermoelectric, spintronic, quantum, MEMS/NEMS, sensor, energy storage and many other devices, which are then used to in automotive, aerospace, medicine, healthcare, security, communications and many other industries. Epitaxy on Si is enabling core technology for most of modern electronic wonders and for many future discoveries. Modern and emerging devices require very sophisticated structures, which are composed of thin layers with various compositions or require creation of low-dimensional structures. When one or more dimensions of a solid material are reduced to nanometre scale, then some of its properties changes dramatically. With reduction in size, novel electrical, optical, thermal, and other properties can be introduced. The resulting structure is then called a low-dimensional structure or a system. Low-dimensional structures are usually classified according to the number of reduced dimensions they have. More precisely, the dimensionality refers to the number of degrees of freedom in the particle momentum. Accordingly, depending on the dimensionality, there are 3D, 2D, 1D and 0D structures. In this talk, an overview and outlook of the group IV semiconductor materials epitaxy will be given.

I.4.3
12:30 Lunch Break    
 
Poster Session : Walter Weber
17:30
Authors : Hyo-Chang Lee, Daehan Choi, Donghwan Kim,Yonghee Jo, J.H. Kim, Euijoon Yoon, TaeWan Kim
Affiliations : Korea Research Institute of Standards and Science Korea Research Institute of Standards and Science Korea Research Institute of Standards and Science Jeonbuk National University Korea Research Institute of Standards and Science Seoul National University Jeonbuk National University

Resume : Contact tailoring for two-dimensional (2D) transition metal dichalcogenides (TMDs) to achieve highperformance devices remains a challenge. Fermi-level pinning at 2D TMD–metal contacts leads to a Schottky barrier for contacts. In addition, when there are no dangling bonds between 2D TMDs and contacts, the contact resistance increases. In this study, Te nanowire (NW) contacts were employed for a MoTe2 p-channel of enhancement mode field-effect transistor (FET) [Applied Surface Science 565 150521 (2021)]. The Te NWs were directly grown on 2D MoTe2 film by metal–organic chemical vapor deposition and selectively etched by a soft plasma etching technique for contact isolation. Using t-Te NW contacts on three-atomic-layer MoTe2, a highly effective field-effect mobility of 543.9 cm2/Vs, as well as ohmic contacts and atomic hybridization, was achieved. These results of t-Te NW electrodes provide a novel device structure for p-type 2D TMD transistors with excellent performances. Further, they offer a practical guideline for wafer-scale 2D TMD-based high-performance electronics and optoelectronics.

I.P.1
17:30
Authors : Daniel Hiller [1], Dirk König [2]
Affiliations : [1] Institute of Applied Physics (IAP), TU Bergakademie Freiberg, Leipziger Str. 23, 09599 Freiberg, Germany [2] Integrated Materials Design Lab (IMDL), Australian National University (ANU), Canberra ACT 2601, Australia

Resume : The SiO2/Al2O3 interface is well known for its high negative fixed charge density, which is widely used in Si technology. When Al2O3 is deposited on bare Si surfaces by atomic layer deposition (ALD), an ultra-thin (approx. 1.5 nm) interfacial Si-oxide layers forms autonomously during the initial phase of the deposition. Alternatively, an interface SiO2 layer can be grown intentionally before ALD by either wet-chemical or thermal treatments. In this presentation we will show that both the presence of a SiO2/Al2O3 interface and its close vicinity to the Si substrate are crucial for the formation of the negative fixed charge [1-4]. It will be demonstrated that unoccupied Al-induced acceptor states in SiO2 capture electrons from the silicon, which causes the negative charge in the dielectric. In addition, electrons from dangling bond defects at the Si/SiO2 can beare captures captured by the Al-acceptor states, which causes causing an electronic deactivation of these interface defects in the process. and therebySuch opportunities for offer excellent interface defect engineering, such as passivated hole contacts at silicon solar cells [3,5]. Last but not least, tIn addition, the capturing of extrinsic electrons into from silicon at Al-acceptor states within the dielectric creates provides free holes in theto silicon as majority carriers and enables thereby a route for modulation doping of silicon nanostructures [1]. [1] D. König et al., Sci. Rep. 7, 46703 (2017) [2] D. Hiller et al., ACS Appl. Mater. Interfaces 10, 30495 (2018) [3] D. Hiller et al., J. Appl. Phys. 125, 015301 (2019) [4] D. Hiller et al., J. Phys. D Appl. Phys. 54, 275304 (2021) [5] D. Hiller et al., Sol. Energy Mater. Sol. Cells 215, 110654 (2020)

I.P.2
17:30
Authors : Masiar Sistani[1], Lukas Wind[1], Walter M. Weber[1] Lada Vukusic[2], Johannes Aberl[2], Moritz Brehm[2] Peter Schweizer[3], Xavier Maeder[3], Johann Michler[3]
Affiliations : [1] Institute of Solid State Electronics, TU Wien, Vienna, Austria [2] Institute of Semiconductor and Solid State Physics, JKU, Linz, Austria [3] Swiss Federal Laboratories for Materials Science and Technology, Thun, Switzerland

Resume : SiGe is among the standard materials in complementary metal-oxide-semiconductor architectures. However, despite considerable efforts, reliability concerns hindered the application of metal-SiGe junctions vital for ”More than Moore” paradigms paving the way for alternative computing via functional diversification of transistors. Here, we report on the systematic structural and electronic properties of Al-SiGe-Al heterostructures, obtained from a thermally induced exchange between ultra-thin Si1−xGex nanosheets and Al pads. Remarkably, no intermetallic phases were formed during the exchange process. Instead, abrupt and flat junctions of high structural quality could be obtained. This finding strongly contrasts the common deficiencies of bulk Al-SiGe junctions, which are plagued by void-formation. A methodical electrical investigation of the obtained Al-SiGe-Al heterostructures was carried out by the integration into omega-gated Schottky barrier transistors, where the source-drain contacts and the channel length are defined by the selective transformation of Si1−xGex into single-elementary Al leads. In this arrangement, a detailed analysis of the electrical transport at elevated temperatures revealed a highly versatile platform with Si1−xGex composition dependent properties ranging from highly transparent contacts to distinct Schottky barriers. Pure Si nanosheets show distinct symmetric effective Schottky barriers (eSBHs) for both electrons and holes, which are highly interesting for reconfigurable electronics. In contrast, for a Ge content of 50%, two transparent junctions were found, which might be used in quantum devices with gate-tunable charge-carrier tunneling for both, electrons and holes. Si0.25Ge0.75 nanosheets revealed strongly asymmetric barriers i.e. a transparent junction for holes and a distinct eSBH for electrons, that due to a more Ge-like band-structure, is potentially interesting for electronics based on negative differential resistance. Finally, due to the vertical Si-Ge-Si stack formed hole-gas, pure Ge nanosheets provide only hole-conduction. In this respect, the ability to tune the transparency of the junction using electrostatic gating might enable key components of quantum computing such as gate-tunable Josephson junctions. Moreover, with respect to photonic applications, the high-quality Al leads formed to all Si1−xGex compositions resemble plasmonic waveguides monolithically embedded with a SiGe detector, where a plasmon-driven hot-electron transfer should enhance the photocurrent. Most importantly, abrupt, robust and reliable metal-SiGe junctions could be a key game-changer for a vast variety of emerging nanoelectronic, optoelectronic and quantum devices, which rely on single-crystalline and monolithic metal-semiconductor-metal heterostructures with high-quality and abrupt interfaces.

I.P.3
17:30
Authors : Piotr Wiśniewski, Jakub Jasiński, Andrzej Mazurak, Bartłomiej Stonio, Romuald B. Beck
Affiliations : Centre for Advanced Materials and Technologies CEZAMAT, Warsaw University of Technology, Warsaw, 02-822, Poland; Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, 00-662, Poland; Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, 00-662, Poland; Centre for Advanced Materials and Technologies CEZAMAT, Warsaw University of Technology, Warsaw, 02-822, Poland, Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, 00-662, Poland; Centre for Advanced Materials and Technologies CEZAMAT, Warsaw University of Technology, Warsaw, 02-822, Poland, Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, 00-662, Poland;

Resume : The Resistive Random Access Memory (RRAM) device generally consists of Metal-Insulator-Metal (MIM) structure. A dielectric layer is sandwiched between two metallic electrodes. Usually, the device needs an initialization through the electroforming process by applying the proper voltage. As a result, conductive filament (CF) is created, forming a path for current flow. This effect may be used to build a new type of non-volatile memory device for information storage, or it may be applied for information processing in new computing paradigms, e.g., in-memory computing and neuromorphic computing. In our previous works, we showed that the proper oxidation process of n++-type Si substrate results in a silicon-oxide layer that can exhibit a resistive switching phenomenon [1][2]. Such devices enable the reversible multistate conversion of resistance controlled by electrical pulses. This work presents the study of different Metal-Oxide-Semiconductor diodes that exhibit the resistive switching effect. Devices consist of an aluminum top electrode and heavily-doped silicon as a bottom electrode. Ultrathin (in the nanometer range) silicon oxide gate dielectric was fabricated using a dry oxidation process. The advantage of this type of structure is full compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) technology. The sample structures were fabricated on silicon wafers with several dopant concentration levels. We investigated the impact of the substrate doping level and doping type on the electrical behavior of the device. Static current-voltage characteristics, as well as small-signal parameters (Capacitance-Voltage, Conductance-Voltage, impedance spectroscopy), were measured and analyzed. We investigated, among others the forming process, the switching cycle of the device operation, retention, and the conductance modulation effect. The charge transport mechanisms in the devices were established based on the electrical measurements. This work aims to compare the investigated types of RRAM devices comprehensively. We show that the oxidation of highly doped n-type and p-type structures can result in an oxide layer exhibiting a resistive switching effect. [1] P. Wiśniewski, J. Jasiński, A. Mazurak, B. Stonio, B. Majkusiak, “Investigation of Electrical Properties of the Al/SiO2/n++-Si Resistive Switching Structures by Means of Static, Admittance, and Impedance Spectroscopy Measurements,” Materials 2021, 14, 6042. DOI : 10.3390/ma14206042. [2] P. Wisniewski, J. Jasinski, A. Mazurak, “Conductance modulation in Al/SiO2/n-Si MIS resistive switching structures,” 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), DOI: 10.1109/EuroSOI-ULIS53016.2021.9560674.

I.P.4
17:30
Authors : Michail Michailow, Oliver Steuer, Slawomir Prucnal, Moazzam Khan, Florian Bärwolf, Yordan Georgiev, Joachim Knoch
Affiliations : Chair of Semiconductor Electronics and Institute of Semiconductor Electronics, RWTH Aachen University, Sommerfeldstr. 18, 52074 Aachen Helmholtz-Zentrum Dresden-Rossendorf, Institute of Ion Beam Physics and Materials Research, 01328 Dresden, Germany

Resume : The power consumption of electronic devices is a significant contributor to the ever-growing global energy demand. Band-to-band Tunnel Field Effect Transistors (TFETs) are a promising steep-slope device concept, which potentially yields a steeper turn-on behavior and leads to a lower operational voltage compared to conventional transistors. However, due to a rather small band-to-band tunneling (BTBT) probability, current realizations of TFETs exhibit a performance substantially inferior to the targeted one. While employing a semiconductor with small band gap increases BTBT it also yields unacceptable leakage currents. As a result, viable performance boosters include a semiconductor heterostructure with a small band gap material only at the BTBT junction, very sharp doping profiles and a nanowire gate-all-around device architecture; the latter requires perfect alignment of the gate electrode with respect to the heterointerface and the dopant profile. Using epitaxial growth, heterostructures with sharp doping profiles that are suitable for vertical gate-all-around nanowire TFETs can be realized. Nevertheless, proper alignment of the gate is very difficult. Here, we present a lateral approach relying on the use of ion-implantation and flash-lamp annealing to generate a doping profile and heterointerface that is self-aligned with respect to a gate electrode. To this end, lateral tunnel-junctions are fabricated with Si0.7Ge0.3 (ca. 10 nm) on Silicon On Insulator as baseline

I.P.5
Start atSubject View AllNum.Add
 
Silicon Quantum Technology : Vihar Georgiev
14:00
Authors : M. Fernando Gonzalez Zalba
Affiliations : Quantum Motion

Resume : The silicon metal-oxide-semiconductor transistor is the workhorse of the microelectronics industry. It is the building block of all major electronic information processing components such as microprocessors, memory chips and telecommunications microcircuits. By shrinking its size generation after generation, the computational performance, memory capacity and information processing speed has increased relentlessly. However, the process of miniaturization is bound to reach its fundamental physical limits in the next decades. New computing paradigms are hence paramount to overcome the technical limitations of silicon technology and to continue increasing the computation performance beyond simple multi-core approaches. Quantum computing offers exponential speed-up over several classical algorithms, and it is hence one of the most sought-after alternatives to conventional computing. However, finding the optimal physical system to process quantum information and scale it up to the large number of qubits necessary to run useful quantum algorithms remains a major challenge. Paradoxically, we are now starting to see that silicon technology itself could offer an optimal platform on which to fabricate scalable quantum circuits: Quantum computing with silicon transistors could profit from the most established industrial technology to fabricate large scale integrated circuits [1], a fact that facilitates the integration with conventional electronics for fast data processing of the binary outputs of the quantum processor [2,3]; all this offering long electron spin coherence times [4], high-fidelity spin readout [5], and one- and two-qubit gates [6-8], the basic physical requirements to build a quantum computer. First, in this talk, I will review the field of silicon-based quantum computing going from the basic physics that govern spin qubits in this material, all the way to the technological implementation, the state-of-the-art and the scaling challenges ahead. Secondly, I will present a series of results on industry-manufactured silicon transistors at milikelvin temperatures that show the technology could provide a platform on to which implement electron spin qubits including our new spin measurement technique that has enabled the first detection of electron spin dynamics in an industry-fabricated device [5,9]. Then, I will present results on how digital, analog, and quantum devices can be combined to perform readout at scale using time- and frequency-multiplexing [3]. Finally, will show a roadmap of how the architecture can be scaled up [10] and, if time allows, fundamental and technological side effects of doing research in silicon quantum computing [11, 12]. [1] M.F. Gonzalez-Zalba, Nat Elect 4 872 (2021) [2] S. Schaal, Nat Elect 2 236 (2019) [3] A. Ruffino, Nat Elect 5 53 (2022) [4] M. Veldhorst, Nature, 526, 410 (2015) [5] G.A.Oakes, arxiv2203.06608 (2022) [6] J. Yoneda, Nat. Nanotech. 13 102 (2018) [7] X. Xue, Nature 601 343 (2022) [8] A. Noiri, Nature 601 338 (2022) [9] V. N. Ciriano-Tejel, PhysRevX Q 2 010353 (2021) [10] O. Crawford, arxiv2201.02877 (2022) [11] L. Cochrane, Phys Rev Lett 128 197701 (2022) [12] T. Lundberg, Phys Rev X 10 041010 (2020)

I.6.1
14:30
Authors : Adam Gali; Péter Udvarhelyi; Anton Pershin; Bálint Somogyi; Gergő Thiering
Affiliations : Department of Atomic Physics, Institute of Physics, Budapest University of Technology and Economics, Műegyetem rakpart 3., H-1111, Budapest, Hungary & Wigner Research Centre for Physics, P.O. Box 49, Budapest, H-1525, Hungary

Resume : Silicon is a technologically mature platforms for hosting quantum defects. Isotope engineering and advanced microfabrication technologies are readily available for this material, which enables improved spin and optical properties of the quantum defects. Several defect emitters were discovered in silicon decades ago, however, the recent isolation of single photon emitter defects [1, 2] revived the interest for their detailed investigation. We apply hybrid DFT method for the identification of various emitters in silicon, report the crucial parameters for their magneto-optical control and provide a microscopic insight for some experimental features. We identify W and G emission centers in silicon [2,3], with zero phonon line (ZPL) energies near the telecommunication O-band. We associate the former with the extended tri-interstitial (I3) defect showing C3 symmetry along the {111} crystal axis. We report that it is the most stable configuration of the so-called I3 configuration. We calculate the electronic structure of the defect in the singlet spin ground and excited state, obtaining a Rydberg-like bound exciton nature for the latter by promoting the electron to the conduction band edge. We calculate ZPL and local vibrational mode energies consistent with experimental findings. We also identify the G-center in silicon, showing optically detected magnetic resonance in its triplet state. We propose the energy position of this triplet state and calculate its zero-field splitting (ZFS) and hyperfine parameters at nearby nuclear spins feasible for quantum register applications. We reveal the microscopic origin of the fine structure in its ZPL emission, associated to a rotational reorientation of the defect. Finally, we propose the C-center as a promising alternative for G-center, with emission in the most favorable L-band for minimizing transmission loss in optical fibers in quantum information applications. We calculate the spin interactions in detail and propose a feasible ODMR and Landau-Zener protocol for the control of both electron and nuclear spins in the defect. We acknowledge the computational resources provided by the DECI resource Eagle HPC based in Poland at Poznan with support from the PRACE aisbl and the funding provided by the National Research, Development, and Innovation Office of Hungary Grant No. KKP129866 of the National Excellence Program of Quantum-Coherent Materials Project, and the Quantum Information National Laboratory supported by the Ministry of Innovation and Technology of Hungary. [1] Broad Diversity of Near-Infrared Single-Photon Emitters in Silicon, A. Durand et al., Phys. Rev. Lett. 126, 083602 [2] Detection of single W-centers in silicon, Y. Baron et al., arXiv preprint arXiv:2108.04283 [3] Identification of a telecom wavelength single photon emitter in silicon, P. Udvarhelyi et al., PRL, 127 (19), 196402

I.6.2
15:00
Authors : Yonder Berencén
Affiliations : Helmholtz-Zentrum Dresden-Rossendorf, Institute of Ion Beam Physics and Materials Research, 01328 Dresden, Germany

Resume : Indistinguishable single-photon sources at telecom wavelengths are the key photonic qubits for transmitting quantum information over long distances in standard optical fibers with minimal transmission losses and high fidelity. This enables secure quantum communication over the quantum internet and, in turn, a modular approach to quantum computing. The monolithic integration of single-photon sources with reconfigurable photonic elements and single-photon detectors in a silicon chip is a key enabling step toward demonstrating scalable quantum hardware such as quantum photonic integrated circuits (QPICs). Nowadays, nearly all the necessary components for QPICs are available such as superconducting single-photon detectors, low-loss photonic waveguides, delay lines, modulators, phase shifters, and low-latency electronics. Yet, the practical implementation of scalable quantum hardware has been largely hampered by the lack of on-chip single-photon emitters in silicon that can be created at desired locations on the nanoscale. Here, we demonstrate two complementary wafer-scale protocols for the quasi-deterministic creation of single G and W telecom-wavelength color centers in silicon with a probability exceeding 50%. Both approaches are fully compatible with current silicon technology and enable the fabrication of single telecom quantum emitters at desired nanoscale positions on a silicon chip. These results unlock a clear and easily exploitable pathway for industrial-scale photonic quantum processors with technology nodes below 100 nm.

I.6.3
15:30 Coffee Break    
Start atSubject View AllNum.Add
 
Doping and Surface Functionalization : Ray Duffy
14:00
Authors : Enrico Napolitani
Affiliations : Dipartimento di Fisica e Astronomia, Università di Padova and CNR-IMM and LNL-INFN, Via Marzolo 8, I-35131 Padova, Italy;

Resume : Doping of group-IV semiconductors at concentrations well above equilibrium solubilities, so called ‘hyperdoping’, is crucial for advanced applications in several fields, such as nanoelectronics, photonics, plasmonics, photovoltaics, quantum computing (solid state state qubits), etc. This talk will review recent results obtained with the Pulsed Laser Melting (PLM) technique which, thanks to the ultra-fast solidification of laser-induced liquid layers, enables record solubilities in most systems. The focus will be on the structural, electrical and optical properties of Ge hyperdoped, both n-type and p-type, on Ge alloyed with Sn, and on Si hyperdoped. We’ll show that, during PLM, several complex phenomena take place, such as dopant clustering (both in the liquid and in the solid phase) and segregation, in-diffusion of contaminants, evolution of extended defects and strain, surface morphology, etc. The stability of the metastable layers upon post-PLM thermal processes need also to be addressed. Beyond record solubilities and the possibility to tailor extended defects and strain, PLM provides also excellent spatial and temperature confinement, with sample heating limited to the uppermost layers and with extremely sharp junctions, making PLM extermely interesting for future device development.

I.7.1
14:30
Authors : D. Nazzari , O. Solfronk, M. Mustajbasic, M. Sistani, W. M. Weber
Affiliations : Institute of Solid-State Electronics, TU Wien, Gußhausstraße 25-25a, 1040 Austria

Resume : Germanium is regarded as one of the most promising channel materials for overcoming the challenges encountered with the extreme scaling of silicon-based metal-oxide-semiconductor field effect transistors (MOSFET), as it benefits from a higher carrier mobility and source injection velocity compared to silicon. Nevertheless, issues arise concerning the passivation of Ge surfaces, which form oxides that show poor electrical properties, are water-soluble and decompose at low temperatures. Moreover, high-k dielectrics deposited directly on cleaned Ge surfaces are characterized by a high density of interface charge traps, deteriorating the overall electrical performances. Several reports have recently shown that nitrides, such as Ge3N4, GeOxNy, AlN, Hf3N4, used as interface materials between Ge and high-k dielectrics, lead to improved electrical characteristics. We illustrate here the preliminary results of a systematic investigation of different interface layers synthetized on Ge using Plasma-Enhanced Atomic Layer Deposition (PEALD). The PEALD reactor used in this study is connected to an Ultra-High Vacuum (UHV) chamber, equipped with an heating stage and several surface analysis tools. This distinctive feature allows to fabricate the interface layers on atomically-clean Ge surfaces, avoiding any kind of impurity. Initially, Ge substrates are carefully prepared in UHV, through a combination of sputtering and annealing cycles, obtaining a well ordered, ultra-flat and oxide-free surface, as confirmed by Atomic Force Microscopy (AFM), Low Energy Electron Diffraction (LEED) and X-ray Photoemission Spectroscopy (XPS). Subsequently, the samples are transferred to the PEALD reactor, where the interface layers of different materials - such as Al2O3, HfO2, ZrO2, AlN, Hf3N4 and GeOxNy - are synthetized directly on top of the Ge surface. While the oxides layers are obtained through standard thermal ALD processes, the nitride ones require an exposure to a N2 plasma. Afterwards, the samples are returned to the UHV chamber, where the stoichiometry of the interfaces is analyzed by XPS. Finally Ti/Au contacts are patterned by means of UV-lithography and evaporated on top of the stacks. Capacitance-voltage (C-V) characteristics of the metal-insulator-semiconductor (MIS) capacitors are measured at different frequencies, extracting the energy profile of the density of trap states at the interface. Preliminary results show a marked reduction of the observed hysteresis, compared to a Ge reference sample with native oxide at the interface. Additionally, nitride-based interface layers determines a lower density of trap states at the interface compared to the case of direct coupling to Al2O3. The results indicate that PEALD is a promising technique for the optimization of the Ge-Insulator interface.

I.7.2
14:45
Authors : Michael Frentzen 1), Dirk König 1;2), Noel Wilck 1), Stefan Scholz 1), Birger Berghoff 1), Daniel Hiller 3), Joachim Knoch,
Affiliations : 1) Institute of Semiconductor Electronics, RWTH Aachen University, 52074 Aachen, Germany; 2) Integrated Materials Design Lab (IMDL), Australian National University, ACT 2601, Australia; 3) Institute of Applied Physics (IAP), Technische Universität Bergakademie Freiberg, 09599 Freiberg, Germany

Resume : UlClassical impurity doping of deeply nanoscale silicon in very large scale integration faces great challenges impairing further device miniaturization. These challenges include dopant out-diffusion, self-purification and inactivation due to increased ionization energies. Based on Density function theory calculations we reported a nanoscale electronic structure shift induced by anions (in particular, oxygen and nitrogen termination) at surfaces (NESSIAS) in ultra small group IV-crystals in previous publications. Depending on the terminating anion at the surface of Si nano crystals the electronic structure is shifted towards higher or lower energies with respect to the bulk levels, resulting in a p-type behavior (nitrogen-termination) or n-type behavior (oxygen-termination), respectively. The predictions of the calculations are supported by measurements performed at Elettra Sincrotrone Trieste using X-ray absorption spectroscopy (XAS), to determine the highest unoccupied state, and ultraviolet photoelectron spectroscopy (UPS), to determine the lowest unoccupied state. The measurements were carried out on 2-dimensional Si nanowells (Nwell) with Si thicknesses in the range of 1.1 nm to 5.0 nm embedded in silicon dioxide or silicon nitride, respectively. While the NESSIAS effect leads to shifting the electronic structure to smaller energies with decreasing Si thickness, quantum confinement counteracts this resulting in an upshift of the electronic structure. Interestingly, the two competing effects yield a minimum at a thickness around 2 nm which is equivalent to a rather large n-type doping concentration. We present our XAS and UPS measurements and an approach to determine the charge carrier density and carrier mobility with electronic transport measurements in ultrathin SiO2-embedded Si Nwells using van der Pauw measurements.

I.7.3
15:00
Authors : Ingmar Ratschinski [1], Soundarya Nagarajan [2], Jens Trommer [2], Thomas Mikolajick [2,3], Daniel Hiller [1]
Affiliations : [1] Institute of Applied Physics (IAP), TU Bergakademie Freiberg, Leipziger Str. 23, 09599 Freiberg, Germany [2] Nanoelectronic Materials Laboratory (NaMLab), Nöthnitzer Str. 64a, 01187 Dresden, Germany [3] Institute of Semiconductors and Microsystems, TU Dresden, Nöthnitzer Str. 64, 01187 Dresden, Germany

Resume : Silicon nanowires (Si NWs) enable maximum gate control over the source-drain current when configured in a gate-all-around field effect transistor (GAA-FET) architecture. However, Si NWs with few nanometers in diameter suffer from severe difficulties with efficient impurity doping due to a multitude of physical and technological problems. These problems include e.g. the undesired diffusion of dopants, segregation or deactivation of dopants at interfaces, dielectric and quantum confinement that inhibit the ionization of an impurity as well as statistical problems when attempting to dope ultra-small Si nanovolumes with an identical amount of a defined number of dopant atoms. Here, we present a novel doping concept for Si NWs comparable to the modulation doping approach known from III-V semiconductors. Modulation doping means that the parent dopant atoms are spatially separated from the volume that is to be doped by embedding them into an adjacent material with a higher bandgap. Based on results from density functional theory (DFT) calculations, we use Al-doped SiO2 shells around the Si nanostructures, which contain unoccupied Al-induced acceptor states that are energetically located below the Si valence band edge. These states can capture electrons from the Si nanostructures, creating a free hole as majority charge carrier. In this presentation first results from the experimental realization of this concept are shown, accompanied by conductivity measurements on modulation-doped and, for reference, undoped Si nanostructures.

I.7.4
15:15
Authors : Philipp M. Wolf (1), Henrik Bruce (1), Wilma Hallén (1), Eduardo Pitthan (1), Zhen Zhang (2), Christian Lavoie (3), Tuan T. Tran (1), and Daniel Primetzhofer (1)
Affiliations : (1) Department of Physics and Astronomy, Uppsala University, Uppsala, Sweden; (2) Solid State Electronics, Department of Electrical Engineering, Uppsala University, Uppsala, Sweden; (3) IBM Thomas J. Watson Research Center, Yorktown Heights, New York, USA

Resume : Due to their low resistivity, transition metal silicides play a decisive role as contact layers and diffusion barriers between semiconductor devices and interconnects in todays integrated circuits [1]. Continued reduction in size of CMOS devices and the associated decrease in thickness of the silicide layer calls for methods with high sensitivity to the outermost atomic layers to investigate potential differences in phase transitions of ultrathin films as compared to thicker films. Here, we utilize one such method, time-of-flight low-energy ion scattering (ToF-LEIS) capable of resolving composition and structure of ultrathin films in a non-destructive manner with sub nm depth resolution [2], to study the phase transition of two relevant silicide systems, ultrathin nickel and titanium silicide films, grown on Si(100) surfaces. A connected preparation chamber equipped with an e-beam evaporator for thin film deposition, a heating filament, an ion sputter gun, an Auger electron spectrometer and a low energy electron diffraction setup, enables us to perform in situ characterizations in our ToF-LEIS setup. Additional ex situ measurements, including time-of-flight medium-energy ion scattering (ToF-MEIS), Rutherford backscattering spectrometry and transmission electron microscopy (TEM) are performed to provide additional information on total areal densities, crystallographic structures and phases present. For Ni silicide films with initial Ni thickness of 3.6 nm, using the above-described approach, we found an unprecedented direct transition from orthorhombic δ-Ni2Si, displaying long-range order covering the whole film thickness, to epitaxial NiSi2-x at 290°C skipping the intermediate NiSi phase observed for thicker films. We propose that the presence of highly ordered δ-Ni2Si enables an effective translation of the crystal characteristics of the substrate to the epitaxial NiSi2-x phase dictating the observed direct transition. Considering previous studies, we further suggest that the ordered δ-Ni2Si phase occurs regardless of the initial Ni film thickness but is limited in thickness by competing orientations of the δ-Ni2Si crystal. Whether the NiSi phase is found absent, depends on whether the formed δ-Ni2Si can consume all deposited Ni or not [3]. To study Ti silicide, a film with initial Ti layer thickness aimed to be 3 nm is annealed in two steps, to 350°C and 500°C, while observing the silicidation process in situ. After annealing the sample to 500°C supplementary ex situ ToF-MEIS and TEM measurements confirm the presence of an epitaxial interface layer with a thickness of 1.5 nm throughout the silicide film at some points extending up to 4 nm into the polycrystalline surface layer. Additionally, roughness of the interface between silicide film and substrate is observed. 1 S.-L. Zhang and Z. Zhang, Met. Films for Electron., Opt. and Magn. Appl., 244–301, 2014 2 M. Draxler et al., Phys. Rev. A, 68, 022901, 2003 3 P. M. Wolf et al., Small, 2106093, 2022

I.7.5
15:30 Coffee Break    
 
Ge-based Nano-Devices : Daniel Hiller
16:00
Authors : Athanasios Dimoulas, Nikitas Siannas, Christina Zacharaki, Polychronis Tsipas
Affiliations : 1. National Centre for Scientific Research “Demokritos”, 15310, Athens, Greece: Athanasios Dimoulas; Nikitas Siannas; Christina Zacharaki; Polychronis Tsipas 2. Department of Physics, National and Kapodistrian University of Athens, 157 84, Athens, Greece: Nikitas Siannas; Christina Zacharaki

Resume : The handling of a large number of inhomogeneous data requires artificial intelligence, energy efficiency and security which will all benefit from advancements in quantum technologies and neuromorphic computing. While at present the latter technologies are developed in parallel along seemingly disconnected routes, it is envisaged that in the future they will merge into a quantum neuromorphic computing [1] platform with combined benefits. Ferroelectric multistate non-volatile memories based on Si-compatible Zr-doped Hafnia (HZO) [2] show promise for low power analog in-memory computing. They appear in different device "flavors" such as Ferroelectric Random Access Memory (FeRAM), Ferroelectric Field Effect Transistors (FeFET) [3] and Ferroelectric Tunnel Junctions (FTJ). The main focus in this presentation will be on the FTJ devices which are resistive two terminal devices with non-destructive reading and excellent integration capability at the back-end of line of CMOS. The work of ferroelectric HZO on Ge (100) substrates prepared by atomic oxygen deposition [4] in an MBE chamber will be presented first, covering performance and reliability characteristics (endurance and retention) [5]. When HZO thickness is scaled below 10nm, as necessary for FTJ devices, ferroelectric loop pinching and reduction of remanent polarization are observed which however recover after field cycling (“wake-up”). This behavior will be explained [6] in terms of depolarization fields in the framework of Landau-Devonshire theory. Subsequently, it will be shown that FTJs with 5 nm HZO and a semiconductor (Ge or Si/STO) bottom electrode behave as analog memories with more than 16 intermediate non-volatile states (corresponding to 4-bit memory cell) which can be accessed by sequential identical or variable width/amplitude pulses. The synaptic conductance weights G can be varied between max and min values in a dynamic range Gmax/Gmin > 5 showing potentiation and depression which emulate a biological synapse. The programming voltage is very low (~ 1V) in full compatibility with voltage scaling trends in advanced CMOS, indicating that our devices are suitable for very low power memory operation. No retention loss was observed at room temperature for >10^4 sec. Finally, future 3D integration schemes directly on Si with side wall FTJs will be discussed which result in very dense cross bar arrays as the main building block of low power analog in memory AI accelerators based on FTJs Acknowledgements: Funded by the EU H2020 project BeFerroSynaptic-871737 References [1] D. Markovic and J. Grollier, Appl. Phys. Lett. 117, 150501 (2020) [2] T.S. Boeske et al, Appl. Phys. Lett. 99, 102903 (2011) [3] C. Zacharaki et al., ACS Appl. Electron. Mater (2022), https://doi.org/10.1021/acsaelm.2c00324 [4] C. Zacharaki et al., Appl. Phys. Lett., 114, 112901 (2019) [5] C. Zacharaki et al., Appl. Phys. Lett, 117, 212905 (2020) [6] N. Siannas et al., Comms. Phys. (2022), accepted

I.8.1
16:30
Authors : Muhammad Bilal Khan1,2, Ahmad Echresh1, Sayantan Ghosh1, Himani Arora1, Phanish Chava1,2, Shima Jazavandi Ghamsari1, Muhammad Moazzam Khan1, Oliver Steuer1, Slawomir Prucnal1, René Hübner1, Lars Rebohle1,2, Shengqiang Zhou1, Manfred Helm1,3,4, Artur Erbe1,3, Yordan M. Georgiev1,3,5
Affiliations : 1 Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum Dresden-Rossendorf (HZDR), Bautzner Landstrasse 400, 01328 Dresden, Germany; 2 International Helmholtz Research School for Nanoelectronic Network, HZDR, Bautzner Landstrasse 400, 01328 Dresden, Germany; 3 Technische Universität Dresden, Centre for Advancing Electronics Dresden (CfAED), 01069 Dresden, Germany; 4 Technische Universität Dresden, Institute of Applied Physics, 01069 Dresden, Germany; 5 Institute of Electronics, Bulgarian Academy of Sciences, 72, Tsarigradsko Chausse Blvd., 1784 Sofia, Bulgaria

Resume : The attractive properties of semiconductor nanowires (NWs) are making them an appealing platform for building a variety of nanoelectronic, optoelectronic, sensing, etc. devices. In the wide range of semiconductor NWs, the ones based on group IV elements deserve a special attention. Beside the extensively studied silicon (Si) and germanium (Ge), their alloys with tin (Sn) – GeSn and SiGeSn – are very promising because of a number of unique properties. Suitable Sn concentrations allow effective bandgap engineering as well as achieving high charge carrier mobility and even a direct Group IV semiconductor for optoelectronic applications. In such a way, the SiGeSn alloy system combines the flexibility of III/V compound semiconductors and heterostructures with the mobility gain of Ge/GaAs hybrid systems and the maturity of the Si processing technology. This makes it ideal for post-Si based nanoelectronic and optoelectronic applications, if SiGeSn heterostructures can successfully be integrated into the well-established Si fabrication platforms. In this talk, the top-down fabrication of Si, Ge and alloy NWs with varying content of the different elements (Si1-x-yGeySnx) will first be presented. Then, their challenging structural and electrical characterisation will be discussed. Here, special attention will be paid to the transmission electron microscopy (TEM) as well as to the Hall Effect measurements using a novel six-contact Hall bar configuration with symmetric contact bars located opposite to each other. This configuration allows reliable evaluation of the electrical properties of even very small nanowires with widths down to 20-30 nm as well as quantification of such parameters as carrier concentration (n), Hall mobility (µH), and resistivity (ρ). Finally, some innovative nanoelectronic devices based on the fabricated NWs will be reviewed, in particular junctionless nanowire transistors (JNTs) and reconfigurable field effect transistors (RFETs). Different configurations of such devices will be discussed together with their structural and electrical characterisation. A special focus will be put on Si JNTs for sensing application as well as on Si, Ge, SiGe, GeSn and SiGeSn JNTs and RFETs for digital logic. Acknowledgments: This work was partially supported by the German Bundesministerium für Bildung und Forschung (BMBF) under the project "ForMikro": Group IV heterostructures for high performance nanoelectronic devices (SiGeSn NanoFETs), Project-ID: 16ES1075, and by the European Union’s Horizon 2020 Research and Innovation programme under the project RADICAL, Grant Agreement No. 899282. We gratefully acknowledge the HZDR Ion Beam Centre and nanofabrication facility NanoFaRo.

I.8.2
17:00 Closing Remarks    

Symposium organizers
Daniel HILLERTU Freiberg

Institute of Applied Physics (IAP), Leipziger Str. 23 - 09599 Freiberg, Germany

daniel.hiller@physik.tu-freiberg.de
Ray DUFFYTyndall National Institute / University College Cork

Lee Maltings, Dyke Parade - Cork T12 SRCP, Ireland

+353 21 234 6644
ray.duffy@tyndall.ie
Vihar GEORGIEVUniversity of Glasgow

School of Engineering, Rankine Building (307B), Glasgow G12 8LT, UK

Vihar.Georgiev@glasgow.ac.uk
Walter WEBERTU Wien

Institute of Solid State Electronics, Professorship of Nanoelectronics, Gußhausstraße 25-25a, A-1040 Wien, Austria

walter.weber@tuwien.ac.at